Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35771 )
Change subject: nb/intel/nehalem: Move romstage boilerplate to a common location ......................................................................
nb/intel/nehalem: Move romstage boilerplate to a common location
Move the mainboard_romstage_entry to a common location and provide mainboard specific callbacks.
Change-Id: Ia827053617cead5d2cf8e9f06cb68c2cbb668ca9 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/35771 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/romstage.c M src/northbridge/intel/nehalem/Makefile.inc M src/northbridge/intel/nehalem/nehalem.h A src/northbridge/intel/nehalem/romstage.c M src/southbridge/intel/ibexpeak/pch.h 6 files changed, 147 insertions(+), 202 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 65abc36..1440c19 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -19,24 +19,12 @@ #include <stdint.h> #include <arch/io.h> #include <device/pci_ops.h> -#include <device/pci_def.h> -#include <cpu/x86/lapic.h> -#include <romstage_handoff.h> -#include <console/console.h> -#include <arch/romstage.h> #include <ec/acpi/ec.h> -#include <timestamp.h> -#include <arch/acpi.h>
-#include "dock.h" #include <southbridge/intel/ibexpeak/pch.h> -#include <southbridge/intel/common/gpio.h> #include <northbridge/intel/nehalem/nehalem.h>
-#include <northbridge/intel/nehalem/raminit.h> -#include <southbridge/intel/ibexpeak/me.h> - -static void pch_enable_lpc(void) +void mainboard_lpc_init(void) { /* EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ @@ -59,6 +47,9 @@
pci_write_config32(PCH_LPC_DEV, ETR3, pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR); + + /* Enable USB Power. We need to do it early for usbdebug to work. */ + ec_set_bit(0x3b, 4); }
const struct southbridge_usb_port mainboard_usb_ports[] = { @@ -79,21 +70,6 @@ { 1, IF1_55F, 7 }, };
-static void rcba_config(void) -{ - southbridge_configure_default_intmap(); - - /* Must set BIT0 (hides performance counters PCI device). - coreboot enables the Rate Matching Hub which makes the UHCI PCI - devices disappear, so BIT5-12 and BIT28 can be set to hide those. */ - RCBA32(FD) = (1 << 28) | (0xff << 5) | 1; - - /* Set reserved bit to 1 */ - RCBA32(FD2) = 1; - - early_usb_init(mainboard_usb_ports); -} - static void set_fsb_frequency(void) { u8 block[5]; @@ -105,86 +81,18 @@ smbus_block_write(0x69, 0, 5, block); }
-void mainboard_romstage_entry(void) +void mainboard_pre_raminit(void) { - u32 reg32; - int s3resume = 0; - const u8 spd_addrmap[4] = { 0x50, 0, 0x51, 0 }; - enable_lapic(); - - nehalem_early_initialization(NEHALEM_MOBILE); - - pch_enable_lpc(); - - /* Enable USB Power. We need to do it early for usbdebug to work. */ - ec_set_bit(0x3b, 4); - - /* Enable GPIOs */ - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - - pch_setup_cir(NEHALEM_MOBILE); - - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - console_init(); - - /* Read PM1_CNT */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); - if (((reg32 >> 10) & 7) == 5) { - u8 reg8; - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); - printk(BIOS_DEBUG, "a2: %02x\n", reg8); - if (!(reg8 & 0x20)) { - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - printk(BIOS_DEBUG, "Bad resume from S3 detected.\n"); - } else { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - s3resume = 1; - } else { - printk(BIOS_DEBUG, - "Resume from S3 detected, but disabled.\n"); - } - } - } - - /* Enable SMBUS. */ - enable_smbus(); - outb((inb(DEFAULT_GPIOBASE | 0x3a) & ~0x2) | 0x20, DEFAULT_GPIOBASE | 0x3a); outb(0x50, 0x15ec); outb(inb(0x15ee) & 0x70, 0x15ee);
- early_thermal_init(); - - timestamp_add_now(TS_BEFORE_INITRAM); - - chipset_init(s3resume); - set_fsb_frequency(); +}
- raminit(s3resume, spd_addrmap); - - timestamp_add_now(TS_AFTER_INITRAM); - - intel_early_me_status(); - - if (s3resume) { - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - } - - romstage_handoff_init(s3resume); +void mainboard_get_spd_map(u8 *spd_addrmap) +{ + spd_addrmap[0] = 0x50; + spd_addrmap[2] = 0x51; } diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 6cee711..b25676b 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -17,25 +17,12 @@ */
#include <stdint.h> -#include <arch/io.h> #include <device/pci_ops.h> -#include <device/pci_def.h> -#include <cpu/x86/lapic.h> -#include <romstage_handoff.h> -#include <console/console.h> -#include <arch/romstage.h> -#include <ec/acpi/ec.h> -#include <timestamp.h> -#include <arch/acpi.h>
-#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/ibexpeak/pch.h> #include <northbridge/intel/nehalem/nehalem.h>
-#include <northbridge/intel/nehalem/raminit.h> -#include <southbridge/intel/ibexpeak/me.h> - -static void pch_enable_lpc(void) +void mainboard_lpc_init(void) { /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, @@ -75,94 +62,12 @@ { 1, IF1_55F, 7 }, };
-static void rcba_config(void) +void mainboard_pre_raminit(void) { - southbridge_configure_default_intmap(); - - /* Must set BIT0 (hides performance counters PCI device). - coreboot enables the Rate Matching Hub which makes the UHCI PCI - devices disappear, so BIT5-12 and BIT28 can be set to hide those. */ - RCBA32(FD) = (1 << 28) | (0xff << 5) | 1; - - /* Set reserved bit to 1 */ - RCBA32(FD2) = 1; - - early_usb_init(mainboard_usb_ports); }
-void mainboard_romstage_entry(void) +void mainboard_get_spd_map(u8 *spd_addrmap) { - u32 reg32; - int s3resume = 0; - const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; - - /* SERR pin is confused on reset. Clear NMI. */ - outb(4, 0x61); - outb(0, 0x61); - - enable_lapic(); - - nehalem_early_initialization(NEHALEM_MOBILE); - - pch_enable_lpc(); - - /* Enable GPIOs */ - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - - pch_setup_cir(NEHALEM_MOBILE); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - console_init(); - - /* Read PM1_CNT */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); - if (((reg32 >> 10) & 7) == 5) { - u8 reg8; - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); - printk(BIOS_DEBUG, "a2: %02x\n", reg8); - if (!(reg8 & 0x20)) { - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - printk(BIOS_DEBUG, "Bad resume from S3 detected.\n"); - } else { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - s3resume = 1; - } else { - printk(BIOS_DEBUG, - "Resume from S3 detected, but disabled.\n"); - } - } - } - - /* Enable SMBUS. */ - enable_smbus(); - - early_thermal_init(); - - timestamp_add_now(TS_BEFORE_INITRAM); - - chipset_init(s3resume); - raminit(s3resume, spd_addrmap); - - timestamp_add_now(TS_AFTER_INITRAM); - - intel_early_me_status(); - - if (s3resume) { - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - } - - romstage_handoff_init(s3resume); + spd_addrmap[0] = 0x50; + spd_addrmap[2] = 0x52; } diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc index 180cc09..3b12bb5 100644 --- a/src/northbridge/intel/nehalem/Makefile.inc +++ b/src/northbridge/intel/nehalem/Makefile.inc @@ -26,6 +26,7 @@ romstage-y += raminit.c romstage-y += raminit_tables.c romstage-y += early_init.c +romstage-y += romstage.c
smm-y += finalize.c
diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index 53743ec..bff5595 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -256,6 +256,8 @@ int bridge_silicon_revision(void); void nehalem_early_initialization(int chipset_type); void nehalem_late_initialization(void); +void mainboard_pre_raminit(void); +void mainboard_get_spd_map(u8 *spd_addrmap);
#endif /* !__SMM__ */
diff --git a/src/northbridge/intel/nehalem/romstage.c b/src/northbridge/intel/nehalem/romstage.c new file mode 100644 index 0000000..8384827 --- /dev/null +++ b/src/northbridge/intel/nehalem/romstage.c @@ -0,0 +1,126 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <console/console.h> +#include <cf9_reset.h> +#include <device/pci_ops.h> +#include <cpu/x86/lapic.h> +#include <timestamp.h> +#include <romstage_handoff.h> +#include "nehalem.h" +#include <arch/romstage.h> +#include <device/pci_def.h> +#include <device/device.h> +#include <northbridge/intel/nehalem/chip.h> +#include <northbridge/intel/nehalem/raminit.h> +#include <southbridge/intel/ibexpeak/pch.h> +#include <southbridge/intel/ibexpeak/me.h> +#include <southbridge/intel/common/pmclib.h> +#include <southbridge/intel/common/gpio.h> + +/* Platform has no romstage entry point under mainboard directory, + * so this one is named with prefix mainboard. + */ +void mainboard_romstage_entry(void) +{ + u32 reg32; + int s3resume = 0; + u8 spd_addrmap[4] = {}; + + enable_lapic(); + + /* TODO, make this configurable */ + nehalem_early_initialization(NEHALEM_MOBILE); + + /* mainboard_lpc_init */ + mainboard_lpc_init(); + + /* Enable GPIOs */ + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); + pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); + + setup_pch_gpios(&mainboard_gpio_map); + + /* TODO, make this configurable */ + pch_setup_cir(NEHALEM_MOBILE); + + southbridge_configure_default_intmap(); + + /* Must set BIT0 (hides performance counters PCI device). + coreboot enables the Rate Matching Hub which makes the UHCI PCI + devices disappear, so BIT5-12 and BIT28 can be set to hide those. */ + RCBA32(FD) = (1 << 28) | (0xff << 5) | 1; + + /* Set reserved bit to 1 */ + RCBA32(FD2) = 1; + + early_usb_init(mainboard_usb_ports); + + /* Initialize console device(s) */ + console_init(); + + /* Read PM1_CNT, DON'T CLEAR IT or raminit will fail! */ + reg32 = inl(DEFAULT_PMBASE + 0x04); + printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); + if (((reg32 >> 10) & 7) == 5) { + u8 reg8; + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + printk(BIOS_DEBUG, "a2: %02x\n", reg8); + if (!(reg8 & 0x20)) { + outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); + printk(BIOS_DEBUG, "Bad resume from S3 detected.\n"); + } else { + if (acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + s3resume = 1; + } else { + printk(BIOS_DEBUG, + "Resume from S3 detected, but disabled.\n"); + } + } + } + + /* Enable SMBUS. */ + enable_smbus(); + + early_thermal_init(); + + timestamp_add_now(TS_BEFORE_INITRAM); + + chipset_init(s3resume); + + mainboard_pre_raminit(); + + mainboard_get_spd_map(spd_addrmap); + + raminit(s3resume, spd_addrmap); + + timestamp_add_now(TS_AFTER_INITRAM); + + intel_early_me_status(); + + if (s3resume) { + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + reg32 = inl(DEFAULT_PMBASE + 0x04); + outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); + } + + romstage_handoff_init(s3resume); +} diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 556b9e0..fbe88a5 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -65,6 +65,7 @@ void early_thermal_init(void); void southbridge_configure_default_intmap(void); void pch_setup_cir(int chipset_type); +void mainboard_lpc_init(void);
enum current_lookup_idx { IF1_F57 = 0, @@ -84,9 +85,11 @@ enum current_lookup_idx current; int oc_pin; }; + void early_usb_init(const struct southbridge_usb_port *portmap);
#ifndef __ROMCC__ +extern const struct southbridge_usb_port mainboard_usb_ports[14]; #include <device/device.h> void pch_enable(struct device *dev); #endif