[coreboot-gerrit] Change in coreboot[master]: soc/amd/cezanne: add downcoring and SMT disable settings to devicetree

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52197 )

Change subject: soc/amd/cezanne: add downcoring and SMT disable settings to devicetree
......................................................................

soc/amd/cezanne: add downcoring and SMT disable settings to devicetree

BUG=b:184162768
TEST=none

Signed-off-by: Felix Held 
Change-Id: Id03454ed2be242bce9497560c089f75046ed7e32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52197
Reviewed-by: Raul Rangel 
Reviewed-by: Marshall Dawson 
Tested-by: build bot (Jenkins) 
---
M src/soc/amd/cezanne/chip.h
M src/soc/amd/cezanne/fsp_m_params.c
2 files changed, 19 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Marshall Dawson: Looks good to me, approved
  Raul Rangel: Looks good to me, approved

diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h
index 455de36..af78ddf 100644
--- a/src/soc/amd/cezanne/chip.h
+++ b/src/soc/amd/cezanne/chip.h
@@ -15,6 +15,18 @@

/* Enable S0iX support */
    bool s0ix_enable;
+
+	enum {
+		DOWNCORE_AUTO = 0,
+		DOWNCORE_1 = 1, /* Run with 1 physical core */
+		DOWNCORE_2 = 3, /* Run with 2 physical cores */
+		DOWNCORE_3 = 4, /* Run with 3 physical cores */
+		DOWNCORE_4 = 6, /* Run with 4 physical cores */
+		DOWNCORE_5 = 8, /* Run with 5 physical cores */
+		DOWNCORE_6 = 9, /* Run with 6 physical cores */
+		DOWNCORE_7 = 10, /* Run with 7 physical cores */
+	} downcore_mode;
+	bool disable_smt; /* disable second thread on all physical cores */
 };

#endif /* CEZANNE_CHIP_H */
diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c
index f24b601..baf4ca8 100644
--- a/src/soc/amd/cezanne/fsp_m_params.c
+++ b/src/soc/amd/cezanne/fsp_m_params.c
@@ -4,10 +4,12 @@
 #include <amdblocks/memmap.h>
 #include <assert.h>
 #include <console/uart.h>
+#include <device/device.h>
 #include <fsp/api.h>
 #include <soc/platform_descriptors.h>
 #include <string.h>
 #include <types.h>
+#include "chip.h"

static void fill_dxio_descriptors(FSP_M_CONFIG *mcfg,
    		const fsp_dxio_descriptor *descs, size_t num)
@@ -51,6 +53,7 @@
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
    FSP_M_CONFIG *mcfg = &mupd->FspmConfig;
+	const struct soc_amd_cezanne_config *config = config_of_soc();

mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_apob_cache();

@@ -62,5 +65,9 @@
    mcfg->serial_port_baudrate = get_uart_baudrate();
    mcfg->serial_port_refclk = uart_platform_refclk();

+	/* 0 is default */
+	mcfg->ccx_down_core_mode = config->downcore_mode;
+	mcfg->ccx_disable_smt = config->disable_smt;
+
    fsp_fill_pcie_ddi_descriptors(mcfg);
 }