Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41049 )
Change subject: nb/intel/i440bx: Refactor ACPI code ......................................................................
Patch Set 6:
(3 comments)
https://review.coreboot.org/c/coreboot/+/41049/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41049/1//COMMIT_MSG@7 PS1, Line 7: nb/intel/i440bx: DSDT upgrade
nb/intel/i440bx: Upgrade DSDT […]
Done
https://review.coreboot.org/c/coreboot/+/41049/1//COMMIT_MSG@15 PS1, Line 15: now it is between TOM and (4GB - CONFIG_ROM_SIZE).
Three separate commits would be nice.
Done
https://review.coreboot.org/c/coreboot/+/41049/3/src/northbridge/intel/i440b... File src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl:
https://review.coreboot.org/c/coreboot/+/41049/3/src/northbridge/intel/i440b... PS3, Line 62: ShiftLeft(0x10000000, 4, Local0)
I know that bit shift math is intentional, and yes because it's 32-bit. […]
Done