Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30712
Change subject: mb/{d41s,d510mo}: Remove references to PCIe port 5 and 6 ......................................................................
mb/{d41s,d510mo}: Remove references to PCIe port 5 and 6
The southbridge has the function disable bits for port 5 and 6 strapped RO to 1 (disable).
Change-Id: I2948935d42b9031d61f9e5b3f06b769e68f5a042 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/foxconn/d41s/devicetree.cb M src/mainboard/intel/d510mo/devicetree.cb 2 files changed, 0 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/30712/1
diff --git a/src/mainboard/foxconn/d41s/devicetree.cb b/src/mainboard/foxconn/d41s/devicetree.cb index 21e8762..75df88e 100644 --- a/src/mainboard/foxconn/d41s/devicetree.cb +++ b/src/mainboard/foxconn/d41s/devicetree.cb @@ -51,7 +51,6 @@ end device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - # (PCIe 5 and 6 not on nm10?) device pci 1d.0 on end # USB device pci 1d.1 on end # USB device pci 1d.2 on end # USB diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb index a80180a..a008610 100644 --- a/src/mainboard/intel/d510mo/devicetree.cb +++ b/src/mainboard/intel/d510mo/devicetree.cb @@ -49,7 +49,6 @@ device pci 1c.1 on end # PCIe 2 device pci 1c.2 on end # PCIe 3 device pci 1c.3 on end # PCIe 4 - # (PCIe 5 and 6 not on nm10?) device pci 1d.0 on end # USB device pci 1d.1 on end # USB device pci 1d.2 on end # USB