Hello Yu-Ping Wu, Julius Werner, You-Cheng Syu, Sj Huang, SJ Huang, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34332
to look at the new patch set (#12).
Change subject: mediatek/mt8183: Support DDR frequency 3600Mbps ......................................................................
mediatek/mt8183: Support DDR frequency 3600Mbps
Add DDR frequency 3600Mbps for EMCP DDR, and fix DDR frequency at 3600Mbps. Using the source code to implement the init setting instead of hard init-sequence. Also, since the mode register value needs to be used at RX gating calibration, we implement the mode register init function and use the global variable to make the mode register value the same.
BUG=b:80501386 BRANCH=none TEST=Memory test pass on EMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 7 files changed, 2,759 insertions(+), 1,927 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/12