Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48577 )
Change subject: soc/intel/braswell: Clean up devicetree settings ......................................................................
soc/intel/braswell: Clean up devicetree settings
Remove unreferenced settings and factor out common settings. Many of these are not mainboard-specific, and all boards use the same value.
Change-Id: Iecae61994a068e8022638a2ad9ca10174427f0a4 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/48577 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Michael Niewöhner foss@mniewoehner.de Reviewed-by: Frans Hendriks fhendriks@eltan.com Reviewed-by: Michał Żygowski michal.zygowski@3mdeb.com Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/facebook/fbg1701/devicetree.cb M src/mainboard/google/cyan/devicetree.cb M src/mainboard/intel/strago/devicetree.cb M src/mainboard/portwell/m107/devicetree.cb M src/mainboard/protectli/vault_bsw/devicetree.cb M src/soc/intel/braswell/chip.c M src/soc/intel/braswell/chip.h M src/soc/intel/braswell/romstage/romstage.c 8 files changed, 11 insertions(+), 73 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Frans Hendriks: Looks good to me, approved Michał Żygowski: Looks good to me, approved Michael Niewöhner: Looks good to me, but someone else must approve
diff --git a/src/mainboard/facebook/fbg1701/devicetree.cb b/src/mainboard/facebook/fbg1701/devicetree.cb index 70e950c..a340fdc 100644 --- a/src/mainboard/facebook/fbg1701/devicetree.cb +++ b/src/mainboard/facebook/fbg1701/devicetree.cb @@ -4,14 +4,9 @@ # Set the parameters for MemoryInit ############################################################
- register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB - - register "PcdMrcInitMmioSize" = "0x0800" register "PcdMrcInitSpdAddr1" = "0xa0" register "PcdMrcInitSpdAddr2" = "0xa2" register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_64MB" - register "PcdApertureSize" = "2" - register "PcdGttSize" = "1" register "PcdDvfsEnable" = "0" register "PcdCaMirrorEn" = "1"
@@ -37,9 +32,6 @@ register "PunitPwrConfigDisable" = "0" # Enable SVID register "ChvSvidConfig" = "1" register "PcdEmmcMode" = "PCH_PCI_MODE" - register "PcdUsb3ClkSsc" = "1" - register "PcdDispClkSsc" = "1" - register "PcdSataClkSsc" = "1" register "PcdEnableSata" = "0" # Disable SATA register "Usb2Port0PerPortPeTxiSet" = "7" register "Usb2Port0PerPortTxiSet" = "5" @@ -65,9 +57,7 @@ register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" - register "PcdSataInterfaceSpeed" = "3" register "PcdPchSsicEnable" = "1" - register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM register "PMIC_I2CBus" = "0" register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb index 91e9795..cec1682 100644 --- a/src/mainboard/google/cyan/devicetree.cb +++ b/src/mainboard/google/cyan/devicetree.cb @@ -7,14 +7,9 @@ # Set the parameters for MemoryInit ############################################################
- register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB - - register "PcdMrcInitMmioSize" = "0x0800" register "PcdMrcInitSpdAddr1" = "0xa0" register "PcdMrcInitSpdAddr2" = "0xa2" register "PcdIgdDvmt50PreAlloc" = "1" - register "PcdApertureSize" = "2" - register "PcdGttSize" = "1" register "PcdDvfsEnable" = "1" register "PcdCaMirrorEn" = "1"
@@ -40,9 +35,6 @@ register "PunitPwrConfigDisable" = "0" # Enable SVID register "ChvSvidConfig" = "SVID_PMIC_CONFIG" register "PcdEmmcMode" = "PCH_PCI_MODE" - register "PcdUsb3ClkSsc" = "1" - register "PcdDispClkSsc" = "1" - register "PcdSataClkSsc" = "1" register "PcdEnableSata" = "0" # Disable SATA register "Usb2Port0PerPortPeTxiSet" = "7" register "Usb2Port0PerPortTxiSet" = "5" @@ -68,9 +60,7 @@ register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" - register "PcdSataInterfaceSpeed" = "3" register "PcdPchSsicEnable" = "1" - register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM register "PMIC_I2CBus" = "1" register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb index 9133787..77b07d2 100644 --- a/src/mainboard/intel/strago/devicetree.cb +++ b/src/mainboard/intel/strago/devicetree.cb @@ -4,14 +4,9 @@ # Set the parameters for MemoryInit ############################################################
- register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB - - register "PcdMrcInitMmioSize" = "0x0800" register "PcdMrcInitSpdAddr1" = "0xa0" register "PcdMrcInitSpdAddr2" = "0xa2" register "PcdIgdDvmt50PreAlloc" = "1" - register "PcdApertureSize" = "2" - register "PcdGttSize" = "1" register "PcdDvfsEnable" = "0" register "PcdCaMirrorEn" = "1"
@@ -37,9 +32,6 @@ register "PunitPwrConfigDisable" = "0" # Enable SVID register "ChvSvidConfig" = "SVID_PMIC_CONFIG" register "PcdEmmcMode" = "PCH_ACPI_MODE" - register "PcdUsb3ClkSsc" = "1" - register "PcdDispClkSsc" = "1" - register "PcdSataClkSsc" = "1" register "PcdEnableSata" = "0" # Disable SATA register "Usb2Port0PerPortPeTxiSet" = "7" register "Usb2Port0PerPortTxiSet" = "5" @@ -65,9 +57,7 @@ register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" - register "PcdSataInterfaceSpeed" = "3" register "PcdPchSsicEnable" = "1" - register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM register "PMIC_I2CBus" = "0" register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" diff --git a/src/mainboard/portwell/m107/devicetree.cb b/src/mainboard/portwell/m107/devicetree.cb index f68b071..d779672 100644 --- a/src/mainboard/portwell/m107/devicetree.cb +++ b/src/mainboard/portwell/m107/devicetree.cb @@ -4,14 +4,9 @@ # Set the parameters for MemoryInit ############################################################
- register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB - - register "PcdMrcInitMmioSize" = "0x0800" register "PcdMrcInitSpdAddr1" = "0xa0" register "PcdMrcInitSpdAddr2" = "0xa2" register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_32MB" - register "PcdApertureSize" = "2" - register "PcdGttSize" = "1" register "PcdDvfsEnable" = "0" register "PcdCaMirrorEn" = "1"
@@ -37,9 +32,6 @@ register "PunitPwrConfigDisable" = "0" # Enable SVID register "ChvSvidConfig" = "1" register "PcdEmmcMode" = "PCH_PCI_MODE" - register "PcdUsb3ClkSsc" = "1" - register "PcdDispClkSsc" = "1" - register "PcdSataClkSsc" = "1" register "PcdEnableSata" = "1" register "Usb2Port0PerPortPeTxiSet" = "7" register "Usb2Port0PerPortTxiSet" = "5" @@ -65,9 +57,7 @@ register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" - register "PcdSataInterfaceSpeed" = "3" register "PcdPchSsicEnable" = "1" - register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM register "PMIC_I2CBus" = "0" register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" diff --git a/src/mainboard/protectli/vault_bsw/devicetree.cb b/src/mainboard/protectli/vault_bsw/devicetree.cb index 94c083d..4b750c0 100644 --- a/src/mainboard/protectli/vault_bsw/devicetree.cb +++ b/src/mainboard/protectli/vault_bsw/devicetree.cb @@ -4,14 +4,9 @@ # Set the parameters for MemoryInit ############################################################
- register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB - - register "PcdMrcInitMmioSize" = "0x0800" register "PcdMrcInitSpdAddr1" = "0xa0" register "PcdMrcInitSpdAddr2" = "0xa2" register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_32MB" - register "PcdApertureSize" = "2" - register "PcdGttSize" = "1" register "PcdDvfsEnable" = "0" register "PcdCaMirrorEn" = "1"
@@ -37,9 +32,6 @@ register "PunitPwrConfigDisable" = "1" # Disable SVID register "ChvSvidConfig" = "SVID_PMIC_CONFIG" register "PcdEmmcMode" = "PCH_DISABLED" - register "PcdUsb3ClkSsc" = "1" - register "PcdDispClkSsc" = "1" - register "PcdSataClkSsc" = "1" register "PcdEnableSata" = "1" register "Usb2Port0PerPortPeTxiSet" = "7" register "Usb2Port0PerPortTxiSet" = "6" @@ -65,9 +57,7 @@ register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" - register "PcdSataInterfaceSpeed" = "3" register "PcdPchSsicEnable" = "1" - register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM register "PMIC_I2CBus" = "0" register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index 25965a0..2adda54 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -81,9 +81,9 @@ params->ChvSvidConfig = config->ChvSvidConfig; params->DptfDisable = config->DptfDisable; params->PcdEmmcMode = config->PcdEmmcMode; - params->PcdUsb3ClkSsc = config->PcdUsb3ClkSsc; - params->PcdDispClkSsc = config->PcdDispClkSsc; - params->PcdSataClkSsc = config->PcdSataClkSsc; + params->PcdUsb3ClkSsc = 1; + params->PcdDispClkSsc = 1; + params->PcdSataClkSsc = 1;
params->Usb2Port0PerPortPeTxiSet = config->Usb2Port0PerPortPeTxiSet; params->Usb2Port0PerPortTxiSet = config->Usb2Port0PerPortTxiSet; @@ -115,14 +115,14 @@ params->Usb3Lane2Ow2tapgen2deemph3p5 = config->Usb3Lane2Ow2tapgen2deemph3p5; params->Usb3Lane3Ow2tapgen2deemph3p5 = config->Usb3Lane3Ow2tapgen2deemph3p5;
- params->PcdSataInterfaceSpeed = config->PcdSataInterfaceSpeed; + params->PcdSataInterfaceSpeed = 3; params->PcdPchUsbSsicPort = config->PcdPchUsbSsicPort; params->PcdPchUsbHsicPort = config->PcdPchUsbHsicPort; - params->PcdPcieRootPortSpeed = config->PcdPcieRootPortSpeed; + params->PcdPcieRootPortSpeed = 0; params->PcdPchSsicEnable = config->PcdPchSsicEnable; params->PcdLogoPtr = config->PcdLogoPtr; params->PcdLogoSize = config->PcdLogoSize; - params->PcdRtcLock = config->PcdRtcLock; + params->PcdRtcLock = 0; params->PMIC_I2CBus = config->PMIC_I2CBus; params->ISPEnable = config->ISPEnable; params->ISPPciDevConfig = config->ISPPciDevConfig; diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 99a1f30..c27ee49 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -41,7 +41,6 @@
struct soc_intel_braswell_config { uint8_t enable_xdp_tap; - uint8_t clkreq_enable;
enum serirq_mode serirq_mode;
@@ -75,14 +74,9 @@ * The following fields come from fsp_vpd.h .aka. VpdHeader.h. * These are configuration values that are passed to FSP during MemoryInit. */ - uint16_t PcdMrcInitTsegSize; - uint16_t PcdMrcInitMmioSize; uint8_t PcdMrcInitSpdAddr1; uint8_t PcdMrcInitSpdAddr2; uint8_t PcdIgdDvmt50PreAlloc; - uint8_t PcdApertureSize; - uint8_t PcdGttSize; - uint8_t PcdLegacySegDecode; uint8_t PcdDvfsEnable; uint8_t PcdCaMirrorEn; /* Command Address Mirroring Enabled */
@@ -110,9 +104,6 @@ uint8_t ChvSvidConfig; uint8_t DptfDisable; uint8_t PcdEmmcMode; - uint8_t PcdUsb3ClkSsc; - uint8_t PcdDispClkSsc; - uint8_t PcdSataClkSsc; uint8_t Usb2Port0PerPortPeTxiSet; uint8_t Usb2Port0PerPortTxiSet; uint8_t Usb2Port0IUsbTxEmphasisEn; @@ -137,14 +128,11 @@ uint8_t Usb3Lane1Ow2tapgen2deemph3p5; uint8_t Usb3Lane2Ow2tapgen2deemph3p5; uint8_t Usb3Lane3Ow2tapgen2deemph3p5; - uint8_t PcdSataInterfaceSpeed; uint8_t PcdPchUsbSsicPort; uint8_t PcdPchUsbHsicPort; - uint8_t PcdPcieRootPortSpeed; uint8_t PcdPchSsicEnable; uint32_t PcdLogoPtr; uint32_t PcdLogoSize; - uint8_t PcdRtcLock; uint8_t PMIC_I2CBus; uint8_t ISPEnable; uint8_t ISPPciDevConfig; diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index a82a4ab..37ee93c 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -113,14 +113,14 @@ config = config_of(dev); printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n");
- upd->PcdMrcInitTsegSize = CONFIG(HAVE_SMI_HANDLER) ? config->PcdMrcInitTsegSize : 0; - upd->PcdMrcInitMmioSize = config->PcdMrcInitMmioSize; + upd->PcdMrcInitTsegSize = CONFIG(HAVE_SMI_HANDLER) ? 8 : 0; + upd->PcdMrcInitMmioSize = 0x800; upd->PcdMrcInitSpdAddr1 = config->PcdMrcInitSpdAddr1; upd->PcdMrcInitSpdAddr2 = config->PcdMrcInitSpdAddr2; upd->PcdIgdDvmt50PreAlloc = config->PcdIgdDvmt50PreAlloc; - upd->PcdApertureSize = config->PcdApertureSize; - upd->PcdGttSize = config->PcdGttSize; - upd->PcdLegacySegDecode = config->PcdLegacySegDecode; + upd->PcdApertureSize = 2; + upd->PcdGttSize = 1; + upd->PcdLegacySegDecode = 0; upd->PcdDvfsEnable = config->PcdDvfsEnable; upd->PcdCaMirrorEn = config->PcdCaMirrorEn; }