[coreboot-gerrit] Change in coreboot[master]: soc/mediatek/mt8183: Tx delay cell should use ddr clock do compute

[huayang duan (Code Review)]

Hello Julius Werner, Hung-Te Lin, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/36990

to look at the new patch set (#2).

Change subject: soc/mediatek/mt8183: Tx delay cell should use ddr clock do compute
......................................................................

soc/mediatek/mt8183: Tx delay cell should use ddr clock do compute

the delay cell result should using the ddr clock pll rate for compute,
should not div 2 more.

BUG=b:80501386,b:142358843
BRANCH=kukui
TEST=Boots correctly on Kukui
Signed-off-by: Huayang Duan

Change-Id: Idf5cce206e248bb327f9a7d27c4f364ef1c68aa1
---
M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
1 file changed, 14 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/36990/2