Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46004 )
Change subject: soc/intel/common/block/acpi: Factor out common pcie_rp_xx_xx.asl ......................................................................
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Patch Set 1: Code-Review+1
IMHO, this would be best done using a SSDT generator for the enabled PCIe ports only.
Yes, totally agree, i will raise a task for internal team to pick and do that going forward. bt i believe for now, this is what look best in terms of reuse of code :) but would be great to generate code based on existing Kconfig option from C code in future.
Not just Kconfig, but also depending on the state of devices at runtime. Why have 24 PCIe root ports in ACPI tables when only 2 of them are present?
Aah, that way, true.
if you want, we could park this CL as well, i just want to share that i have tried my best to address the possible common code 😊 before adding ADL ACPI code