[coreboot-gerrit] Change in coreboot[master]: nb/amd/amdfam10/bootblock.c: Use HT defined register values

[Michał Żygowski (Code Review)]

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62097 )

Change subject: nb/amd/amdfam10/bootblock.c: Use HT defined register values
......................................................................

nb/amd/amdfam10/bootblock.c: Use HT defined register values

Signed-off-by: Michał Żygowski 
Change-Id: I882afcf20be110d9f1e8185ece1f42c4792e7d5e
---
M src/northbridge/amd/amdfam10/bootblock.c
1 file changed, 23 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/62097/1

diff --git a/src/northbridge/amd/amdfam10/bootblock.c b/src/northbridge/amd/amdfam10/bootblock.c
index f595b70..da4eb03 100644
--- a/src/northbridge/amd/amdfam10/bootblock.c
+++ b/src/northbridge/amd/amdfam10/bootblock.c
@@ -16,6 +16,7 @@

#include <stdint.h>
 #include <arch/bootblock.h>
+#include <device/hypertransport.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <limits.h>
@@ -42,6 +43,15 @@
    /* CPU on bus 0xff and 0xfe now. For now on we can use CONFIG_CBB and CONFIG_CDB. */
 }

+static bool pci_cap_is_ht_primary(u8 pos)
+{
+	u16 flags = pci_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS);
+	if ((flags >> HT_CMD_CAP_OFFSET) == HT_CMD_CAP_PRIMARY)
+		return true;
+	else
+		return false;
+}
+
 static void enumerate_ht_chain(void)
 {

@@ -90,7 +100,7 @@
    		flags = pci_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS);
    		pci_write_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS, flags);
    		flags = pci_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS);
-			if ((flags >> 13) == 0) {
+			if (pci_cap_is_ht_primary(pos)) {
    			unsigned int count;
    			unsigned int ctrl, ctrl_off;
    			pci_devfn_t devx;
@@ -114,26 +124,26 @@
    					goto out;
    			}

-				flags &= ~0x1f;
-				flags |= next_unitid & 0x1f;
-				count = (flags >> 5) & 0x1f;
+				flags &= ~HT_PRIMARY_BASE_UNIT_ID_MASK;
+				flags |= next_unitid & HT_PRIMARY_BASE_UNIT_ID_MASK;
+				count = (flags >> HT_PRIMARY_UNIT_COUNT_OFFSET) & HT_PRIMARY_UNIT_COUNT_MASK;
    			devx = PCI_DEV(0, next_unitid, 0);
    			next_unitid += count;

pci_write_config16(PCI_DEV(0, 0, 0), pos + PCI_CAP_FLAGS, flags);

/* Test for end of chain */
-				ctrl_off = ((flags >> 10) & 1)?
-					PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
+				ctrl_off = (flags & HT_CMD_MASTER_OR_SLAVE) ?
+					PCI_HT_CAP_HOST_CTRL : PCI_HT_CAP_SLAVE_CTRL1;

do {
    				ctrl = pci_read_config16(devx, pos + ctrl_off);
    				/* Is this the end of the hypertransport chain? */
-					if (ctrl & (1 << 6)) {
+					if (ctrl & HT_LINK_CTRL_END_OF_CHAIN) {
    					goto out;
    				}

-					if (ctrl & ((1 << 4) | (1 << 8))) {
+					if (ctrl & (HT_LINK_CTRL_LINK_FAIL | HT_LINK_CTRL_CRC_UNRECOV_ERR)) {
    					/*
    					 * Either the link has failed, or we have
    					 * a CRC error.
@@ -141,15 +151,15 @@
    					 * retrain, so lets knock it down and see
    					 * if its transient
    					 */
-						ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc
+						ctrl |= (HT_LINK_CTRL_LINK_FAIL | HT_LINK_CTRL_CRC_UNRECOV_ERR);
    					pci_write_config16(devx, pos + ctrl_off, ctrl);
    					ctrl = pci_read_config16(devx, pos + ctrl_off);
-						if (ctrl & ((1 << 4) | (1 << 8))) {
+						if (ctrl & (HT_LINK_CTRL_LINK_FAIL | HT_LINK_CTRL_CRC_UNRECOV_ERR)) {
    						/* Can not clear the error */
    						break;
    					}
    				}
-				} while ((ctrl & (1 << 5)) == 0);
+				} while (!(ctrl & HT_LINK_CTRL_INIT_COMPLETE));

break;
    		}
@@ -163,8 +173,8 @@
    	    (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) {
    		u16 flags;
    		flags = pci_read_config16(PCI_DEV(0,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS);
-			flags &= ~0x1f;
-			flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f;
+			flags &= ~HT_PRIMARY_BASE_UNIT_ID_MASK;
+			flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & HT_PRIMARY_BASE_UNIT_ID_MASK;
    		pci_write_config16(PCI_DEV(0, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags);
    	}
    }