[coreboot-gerrit] Change in coreboot[master]: nb/i945: Move DEFAULT_MCHBAR to Kconfig

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45613 )

Change subject: nb/i945: Move DEFAULT_MCHBAR to Kconfig
......................................................................

nb/i945: Move DEFAULT_MCHBAR to Kconfig

Change-Id: If7aab904a92ddf741e7032fd111c945633d7c1d6
Signed-off-by: Elyes HAOUAS 
---
M src/northbridge/intel/i945/Kconfig
M src/northbridge/intel/i945/acpi/i945.asl
M src/northbridge/intel/i945/early_init.c
M src/northbridge/intel/i945/i945.h
4 files changed, 9 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/45613/1

diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index d6498f1..0499a7c 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -15,6 +15,10 @@
    select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
    select PARALLEL_MP

+config DEFAULT_MCHBAR
+	hex
+	default 0xfed14000
+
 config VBOOT
    select VBOOT_STARTS_IN_BOOTBLOCK
    select VBOOT_SEPARATE_VERSTAGE
diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl
index 789225c..76a50f0 100644
--- a/src/northbridge/intel/i945/acpi/i945.asl
+++ b/src/northbridge/intel/i945/acpi/i945.asl
@@ -39,7 +39,7 @@

Name (PDRS, ResourceTemplate() {
    	Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000)
-		Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
+		Memory32Fixed(ReadWrite, CONFIG_DEFAULT_MCHBAR, 0x00004000)
    	Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
    	Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
    	Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index b04a2f594..0bdcd17 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -145,7 +145,7 @@
    printk(BIOS_DEBUG, "Setting up static northbridge registers...");
    /* Set up all hardcoded northbridge BARs */
    pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1);
-	pci_write_config32(HOST_BRIDGE, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
+	pci_write_config32(HOST_BRIDGE, MCHBAR, (uintptr_t)CONFIG_DEFAULT_MCHBAR | 1);
    pci_write_config32(HOST_BRIDGE, DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
    pci_write_config32(HOST_BRIDGE, X60BAR, DEFAULT_X60BAR | 1);

diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index 4b79b2b..96623be 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -6,10 +6,8 @@
 /* Northbridge BARs */
 #define DEFAULT_X60BAR		0xfed13000
 #ifndef __ACPI__
-#define DEFAULT_MCHBAR		((u8 *)0xfed14000)	/* 16 KB */
 #define DEFAULT_DMIBAR		((u8 *)0xfed18000)	/* 4 KB */
 #else
-#define DEFAULT_MCHBAR		0xfed14000	/* 16 KB */
 #define DEFAULT_DMIBAR		0xfed18000	/* 4 KB */
 #endif
 #define DEFAULT_EPBAR		0xfed19000	/* 4 KB */
@@ -99,9 +97,9 @@
  * MCHBAR
  */

-#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x))))
-#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x))))
-#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x))))
+#define MCHBAR8(x) (*((volatile u8 *)(CONFIG_DEFAULT_MCHBAR + (x))))
+#define MCHBAR16(x) (*((volatile u16 *)(CONFIG_DEFAULT_MCHBAR + (x))))
+#define MCHBAR32(x) (*((volatile u32 *)(CONFIG_DEFAULT_MCHBAR + (x))))

/* Chipset Control Registers */
 #define FSBPMC3		0x40	/* 32bit */