[coreboot-gerrit] Change in coreboot[master]: google/lars: Add sdmode-delay property for max98357a

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/23568

Change subject: google/lars: Add sdmode-delay property for max98357a
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google/lars: Add sdmode-delay property for max98357a

Adapted from Chromium commit:
af3ec09 [Lars: Add sdmode-delay device property for maxim98357a]

Add "sdmode-delay" as a device property for the maxim98357a codec.
This speaker amp requires both SFRM & BCLK to active and stable
before it is unmuted. If there is a BCLK and no SFRM,
that results in a pop noise.

Adding a configurable delay parameter for all Skylake platforms
to allow sufficient time for the BCLK & SFRM on I2S to be stable
before the amp unmutes itself to avoid a pop noise at the start of playback.
Setting the delay to 5ms since the observed delay between SFRM and unmuting
of the amp is around 2ms.

Adaptation needed to account for parameters having moved
from mainboard.asl to devicetree in upstream tree.

Original-Change-Id: I1fff4f86ff816e907553e7a6f1d05713f9d85084
Original-Signed-off-by: Rohit Ainapure 
Original-Reviewed-by: Aaron Durbin

Change-Id: I8a1c52ccdb08df9a4ab293e12bb266309e08737b
Signed-off-by: Matt DeVillier 
---
M src/mainboard/google/lars/devicetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/23568/1

diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index 64f2a61..344d4b7 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -284,6 +284,7 @@
    	device pci 1f.3 on
    		chip drivers/generic/max98357a
    			register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)"
+				register "sdmode_delay" = "5"
    			device generic 0 on end
    		end
    	end # Intel HDA