Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/26730
Change subject: soc/intel/common: Allow RX level/Edge configuartion to be set for IOAPIC IRQ mode ......................................................................
soc/intel/common: Allow RX level/Edge configuartion to be set for IOAPIC IRQ mode
GPIO configuration in IOAPIC mode is not limited to only LEVEL trigger mode. This implementation allows level/edge/ either/none trigger configuration to be set for a GPIO in IOAPIC mode with RX Invert configuration.
Change-Id: I4e1f009489f2d8338ae94b78d7e9eb3f88a85daa Signed-off-by: Aamir Bohra aamir.bohra@intel.com --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/26730/1
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 244c680..13d08e7 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -278,8 +278,8 @@ * on its own end. One just needs to pass an active high message into the * ITSS. */ -#define PAD_CFG_GPI_APIC_LOW(pad, pull, rst) \ - PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, INVERT) +#define PAD_CFG_GPI_APIC_LOW(pad, pull, rst, trig) \ + PAD_CFG_GPI_APIC(pad, pull, rst, trig, INVERT)
#define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) \ PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, NONE)