Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/22982
Change subject: [UNTESTED]nb/intel/sandybridge: Use common mrc cache functions ......................................................................
[UNTESTED]nb/intel/sandybridge: Use common mrc cache functions
This uses the functions in include/mrc_cache.h instead of northbidge/intel/common/mrc_cache.h
Change-Id: I46002c0b19a55d855286eb8b0ca934ef7ca7fe09 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/Makefile.inc M src/northbridge/intel/sandybridge/raminit.c 3 files changed, 12 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/22982/1
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 043e8de..a1f21a2 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -16,7 +16,7 @@
config NORTHBRIDGE_INTEL_SANDYBRIDGE bool - select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE + select CACHE_MRC_SETTINGS select CPU_INTEL_MODEL_206AX select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI @@ -24,7 +24,7 @@
config NORTHBRIDGE_INTEL_IVYBRIDGE bool - select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE + select CACHE_MRC_SETTINGS select CPU_INTEL_MODEL_306AX select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 846d31b..1470353 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -45,16 +45,4 @@
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
-ifneq ($(CONFIG_CHROMEOS),y) -$(obj)/mrc.cache: $(obj)/config.h - dd if=/dev/zero count=1 \ - bs=$(shell printf "%d" $(CONFIG_MRC_CACHE_SIZE) ) | \ - tr '\000' '\377' > $@ - -cbfs-files-y += mrc.cache -mrc.cache-file := $(obj)/mrc.cache -mrc.cache-align := 0x10000 -mrc.cache-type := mrc_cache -endif - endif diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 12384b4..4ec1adf 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -23,7 +23,7 @@ #include <cbmem.h> #include <halt.h> #include <timestamp.h> -#include <northbridge/intel/common/mrc_cache.h> +#include <mrc_cache.h> #include <southbridge/intel/bd82x6x/me.h> #include <southbridge/intel/common/smbus.h> #include <cpu/x86/msr.h> @@ -35,6 +35,8 @@ #include "raminit_common.h" #include "sandybridge.h"
+#define MRC_CACHE_VERSION 0 + /* FIXME: no ECC support. */ /* FIXME: no support for 3-channel chipsets. */
@@ -292,7 +294,8 @@ static void save_timings(ramctr_timing *ctrl) { /* Save the MRC S3 restore data to cbmem */ - store_current_mrc_cache(ctrl, sizeof(*ctrl)); + mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, ctrl, + sizeof(*ctrl)); }
static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, @@ -311,7 +314,7 @@ ramctr_timing ctrl; int fast_boot; spd_raw_data spds[4]; - struct mrc_data_container *mrc_cache; + struct region_device rdev; ramctr_timing *ctrl_cached; struct cpuid_result cpures; int err; @@ -347,8 +350,9 @@ early_thermal_init();
/* try to find timings in MRC cache */ - mrc_cache = find_current_mrc_cache(); - if (!mrc_cache || (mrc_cache->mrc_data_size < sizeof(ctrl))) { + int cache_not_found = mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, + &rdev); + if (cache_not_found || (region_device_sz(&rdev) < sizeof(ctrl))) { if (s3resume) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); @@ -356,7 +360,7 @@ } ctrl_cached = NULL; } else { - ctrl_cached = (ramctr_timing *)mrc_cache->mrc_data; + ctrl_cached = rdev_mmap_full(&rdev); }
/* verify MRC cache for fast boot */