[coreboot-gerrit] Change in coreboot[master]: soc/mediatek/mt8192: Do dramc rx datlat training

[CK HU (Code Review)]

Hello Duan huayang,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/44721

to review the following change.

Change subject: soc/mediatek/mt8192: Do dramc rx datlat training
......................................................................

soc/mediatek/mt8192: Do dramc rx datlat training

Signed-off-by: Huayang Duan 
Change-Id: I9a426e1273dceae3a739bbbfc36db44d3ba9140d
---
M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c
M src/soc/mediatek/mt8192/dramc_pi_main.c
2 files changed, 54 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/44721/1

diff --git a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c
index 602e61d..9ccedf1 100644
--- a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c
+++ b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c
@@ -1408,6 +1408,36 @@
    dramc_set_broadcast(bc_bak);
 }

+static void dramc_dle_factor_handler(u8 chn, u8 value)
+{
+	u8 datlat_dsel = 0, dlecg_ext1 = 0, dlecg_ext2 = 0, dlecg_ext3 = 0;
+
+	if (READ32_BITFIELD(&ch[chn].phy_ao.shu_misc_rx_pipe_ctrl,
+		SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN))
+		datlat_dsel = value;
+	else
+		datlat_dsel = (value < 1) ? value : value - 1;
+
+	SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rdat,
+		MISC_SHU_RDAT_DATLAT, value,
+		MISC_SHU_RDAT_DATLAT_DSEL, datlat_dsel,
+		MISC_SHU_RDAT_DATLAT_DSEL_PHY, datlat_dsel);
+
+	dlecg_ext1 = (value >= 8) ? 1 : 0;
+	dlecg_ext2 = (value >= 14) ? 1 : 0;
+	dlecg_ext3 = (value >= 19) ? 1 : 0;
+
+	SET32_BITFIELDS(&ch[chn].ao.shu_rx_cg_set0,
+		SHU_RX_CG_SET0_READ_START_EXTEND1, dlecg_ext1,
+		SHU_RX_CG_SET0_DLE_LAST_EXTEND1, dlecg_ext1,
+		SHU_RX_CG_SET0_READ_START_EXTEND2, dlecg_ext2,
+		SHU_RX_CG_SET0_DLE_LAST_EXTEND2, dlecg_ext2,
+		SHU_RX_CG_SET0_READ_START_EXTEND3, dlecg_ext3,
+		SHU_RX_CG_SET0_DLE_LAST_EXTEND3, dlecg_ext3);
+
+	dramc_phy_reset(chn);
+}
+
 static u8 rxdqs_gating_get_tx_dly_min(dram_freq_grp freq_group,
    struct rxdqs_gating_best_win *rxdqs_best_win)
 {
@@ -2713,3 +2743,25 @@
    	update_tx_tracking(chn, rk, cali_type, dq_pi, dqm_pi);
    }
 }
+
+void dramc_rx_datlat_cal(const struct ddr_cali* cali)
+{
+	u8 chn = cali->chn;
+	u8 rank = cali->rank;
+	u8 datlat = cali->params->rx_datlat[chn][rank];
+	dramc_dbg("best_step = %d\n", datlat);
+
+	dramc_engine2_init(chn, rank);
+	dramc_dle_factor_handler(chn, datlat);
+}
+
+void dramc_dual_rank_rx_datlat_cal(const struct ddr_cali* cali)
+{
+	u8 chn = cali->chn;
+	u8 datlat_1 = cali->params->rx_datlat[chn][0];
+	u8 datlat_2 = cali->params->rx_datlat[chn][1];
+	u8 final_datlat = MAX(datlat_1, datlat_2);
+
+	dramc_dle_factor_handler(chn, final_datlat);
+}
+
diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c
index f724e54..9df4285 100644
--- a/src/soc/mediatek/mt8192/dramc_pi_main.c
+++ b/src/soc/mediatek/mt8192/dramc_pi_main.c
@@ -287,9 +287,11 @@
    		switch_write_dbi_settings(cali, DBI_OFF);
    	}

+		dramc_rx_datlat_cal(cali);
    	dramc_rx_window_perbit_cal(cali, RX_WIN_TEST_ENG);
    }
    dramc_rx_dqs_gating_post_process(cali, txdly_min, txdly_max);
+	dramc_dual_rank_rx_datlat_cal(cali);
 }

static void dramc_calibration_all_channels(struct ddr_cali *cali)