Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35542 )
Change subject: soc/intel/skylake: devicetrice: introduce PchHdaVcType parameter for FSP ......................................................................
soc/intel/skylake: devicetrice: introduce PchHdaVcType parameter for FSP
Set the FSP Parameter PchHdaVcType from devicetree if needed for a variant.
Signed-off-by: Michael Niewöhner foss@mniewoehner.de Change-Id: Ibafc3b6bd2495658f2bd634218042ec413a89f5e --- M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/asrock/h110m/ramstage.c M src/mainboard/intel/kblrvp/ramstage.c M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/ramstage.c M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/chip_fsp20.c 8 files changed, 7 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/35542/1
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 572cd6a..f6a0bcf 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -55,6 +55,7 @@ register "PmTimerDisabled" = "0" register "EnableAzalia" = "1" register "DspEnable" = "0" + register "PchHdaVcType" = "0x01"
register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/mainboard/asrock/h110m/ramstage.c b/src/mainboard/asrock/h110m/ramstage.c index c93e84c..a247b72 100644 --- a/src/mainboard/asrock/h110m/ramstage.c +++ b/src/mainboard/asrock/h110m/ramstage.c @@ -24,6 +24,4 @@ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
params->CdClock = 3; - /* Enable Virtual Channel 1 */ - params->PchHdaVcType = 0x1; } diff --git a/src/mainboard/intel/kblrvp/ramstage.c b/src/mainboard/intel/kblrvp/ramstage.c index ad55c26..a19e96e 100644 --- a/src/mainboard/intel/kblrvp/ramstage.c +++ b/src/mainboard/intel/kblrvp/ramstage.c @@ -25,9 +25,6 @@ * dependencies during hardware initialization. */ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); params->CdClock = 3; - - /* Enable Virtual Channel 1 */ - params->PchHdaVcType = 0x1; }
static void ioexpander_init(void *unused) diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index 2a1cb8a..43c16e3 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -30,6 +30,7 @@ register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "SaGv" = "SaGv_Enabled" + register "PchHdaVcType" = "0x01"
register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/mainboard/supermicro/x11-lga1151-series/ramstage.c b/src/mainboard/supermicro/x11-lga1151-series/ramstage.c index 677a10f..a16678e 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/ramstage.c +++ b/src/mainboard/supermicro/x11-lga1151-series/ramstage.c @@ -20,9 +20,4 @@ /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); - - // TODO: on x11ssm FSP does not crash as in x11ssh; even when explicitly setting to 0x0 - // probably can be removed here - /* This must be one, otherwise FSP crashes ... */ - params->PchHdaVcType = 0x1; } diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index 1039f7a..02db50c 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -30,6 +30,9 @@ register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "0"
+ # FIXME: find out why FSP crashes without this + register "PchHdaVcType" = "0x01" + device domain 0 on device pci 01.0 on end # unused device pci 01.1 on # PCIE Slot (JPCIE1) diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index fee14d8..dc263a2 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -207,6 +207,7 @@ /* Audio related */ u8 EnableAzalia; u8 DspEnable; + u8 PchHdaVcType;
/* * I/O Buffer Ownership: diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index d1d7d6f..4fa34b0 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -361,6 +361,7 @@ params->PchIshEnable = dev ? dev->enabled : 0;
params->PchHdaEnable = config->EnableAzalia; + params->PchHdaVcType = config->PchHdaVcType; params->PchHdaIoBufferOwnership = config->IoBufferOwnership; params->PchHdaDspEnable = config->DspEnable; params->Device4Enable = config->Device4Enable;