[coreboot-gerrit] Change in coreboot[master]: mb/intel/saddlebrook: Enable Chipset_lockdown coreboot config

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36451 )

Change subject: mb/intel/saddlebrook: Enable Chipset_lockdown coreboot config
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Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/36451/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/36451/1//COMMIT_MSG@12 
PS1, Line 12: verified MRC is restored on warm, cold,
            : 	resume boot path's
> What does that have to do with the lockdown?

Lockdown can affect everything. Especially in the presence of undocumented
blobs. For instance, if locking happens too early, a register write may fail
silently. In this case, I'd assume that the MRC cache can't be written if
some flash locking is out of sync.