[coreboot-gerrit] Change in coreboot[master]: src/superio/nuvoton/nct5104d: soft reset GPIO

[Piotr Kleinschmidt (Code Review)]

Piotr Kleinschmidt has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35482 )

Change subject: src/superio/nuvoton/nct5104d: soft reset GPIO
......................................................................

src/superio/nuvoton/nct5104d: soft reset GPIO

So far, only hard power off could reset GPIOs state to defaults:
IN, Open-drain. Now, defaults are set with every boot to ensure
that GPIOS are not in uknown/unwanted state.

Change-Id: I67878dbab2ddf0deaaa8f5d79416368c6164ba1d
Signed-off-by: Piotr Kleinschmidt 
---
M src/superio/nuvoton/nct5104d/nct5104d.h
M src/superio/nuvoton/nct5104d/superio.c
2 files changed, 24 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/35482/1

diff --git a/src/superio/nuvoton/nct5104d/nct5104d.h b/src/superio/nuvoton/nct5104d/nct5104d.h
index 707e94a..6826bb6 100644
--- a/src/superio/nuvoton/nct5104d/nct5104d.h
+++ b/src/superio/nuvoton/nct5104d/nct5104d.h
@@ -21,15 +21,25 @@
 #include <device/pnp_type.h>

/* SIO global configuration */
+#define LDN_SELECT_CR07     0x07
 #define IRQ_TYPE_SEL_CR10   0x10     /* UARTA,UARTB */
 #define IRQ_TYPE_SEL_CR11   0x11     /* SMI,UARTC,UARTD,WDTO */
 #define GLOBAL_OPTION_CR26  0x26
 #define CR26_LOCK_REG       (1 << 4) /* required to access CR10/CR11 */

+/* LDN 0x07 specific registers */
+#define NCT5104D_GPIO0_IO   0xE0
+#define NCT5104D_GPIO1_IO   0xE4
+
+/* LDN 0x0F specific registers */
+#define NCT5104D_GPIO0_PP_OD   0xE0
+#define NCT5104D_GPIO1_PP_OD   0xE1
+
 /* Logical Device Numbers (LDN). */
 #define NCT5104D_FDC        0x00 /* FDC - not pinned out */
 #define NCT5104D_SP1        0x02 /* UARTA */
 #define NCT5104D_SP2        0x03 /* UARTB */
+#define NCT5104D_GPIO       0x07 /* GPIO In-Out configuration */
 #define NCT5104D_GPIO_WDT   0x08 /* GPIO WDT Interface */
 #define NCT5104D_GPIO_PP_OD 0x0F /* GPIO Push-Pull / Open drain select  */
 #define NCT5104D_SP3        0x10 /* UARTC */
diff --git a/src/superio/nuvoton/nct5104d/superio.c b/src/superio/nuvoton/nct5104d/superio.c
index 40d1200..53eb99d 100644
--- a/src/superio/nuvoton/nct5104d/superio.c
+++ b/src/superio/nuvoton/nct5104d/superio.c
@@ -106,6 +106,19 @@
    pnp_write_config(dev, 0x1c, reg);
 }

+static void reset_gpio(struct device *dev)
+{
+	/* Soft reset GPIOs to default state: IN, Open-drain */
+
+	pnp_write_config(dev, LDN_SELECT_CR07, NCT5104D_GPIO);
+	pnp_write_config(dev, NCT5104D_GPIO0_IO, 0xFF);
+	pnp_write_config(dev, NCT5104D_GPIO1_IO, 0xFF);
+
+	pnp_write_config(dev, LDN_SELECT_CR07, NCT5104D_GPIO_PP_OD);
+	pnp_write_config(dev, NCT5104D_GPIO0_PP_OD, 0xFF);
+	pnp_write_config(dev, NCT5104D_GPIO1_PP_OD, 0xFF);
+}
+
 static void nct5104d_init(struct device *dev)
 {
    struct superio_nuvoton_nct5104d_config *conf = dev->chip_info;
@@ -127,6 +140,7 @@
    	break;
    case NCT5104D_GPIO0:
    case NCT5104D_GPIO1:
+		reset_gpio(dev);
    	route_pins_to_uart(dev, false);
    	break;
    default: