[coreboot-gerrit] Change in coreboot[master]: nb/intel/sandybridge: Add Xeon E3-1200 (v1) hostbridge PCI ID

[Jonathan Kollasch (Code Review)]

Jonathan Kollasch has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38865 )

Change subject: nb/intel/sandybridge: Add Xeon E3-1200 (v1) hostbridge PCI ID
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nb/intel/sandybridge: Add Xeon E3-1200 (v1) hostbridge PCI ID

Change-Id: I70187d09ecdaa8149299cdd8f6f8fc9517b05e15
Signed-off-by: Jonathan A. Kollasch 
---
M src/northbridge/intel/sandybridge/northbridge.c
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/38865/1

diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index a9b1c25..d679eaa 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -472,6 +472,12 @@
    .device = 0x0104, /* Sandy bridge */
 };

+static const struct pci_driver mc_driver_108 __pci_driver = {
+	.ops    = &mc_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = 0x0108, /* Sandy bridge */
+};
+
 static const struct pci_driver mc_driver_150 __pci_driver = {
    .ops    = &mc_ops,
    .vendor = PCI_VENDOR_ID_INTEL,