[coreboot-gerrit] Change in ...coreboot[master]: {gm45,pineview,sandybridge,x4x}: Use {full,system}_reset() function

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32608

Change subject: {gm45,pineview,sandybridge,x4x}: Use {full,system}_reset() function
......................................................................

{gm45,pineview,sandybridge,x4x}: Use {full,system}_reset() function

Use already defined system_reset() and full_reset() functions.

Change-Id: Ic29fab70cf7f23d49c3eeeb97c984c523f973972
Signed-off-by: Elyes HAOUAS 
---
M src/northbridge/intel/gm45/early_reset.c
M src/northbridge/intel/pineview/raminit.c
M src/northbridge/intel/sandybridge/romstage.c
M src/northbridge/intel/x4x/raminit.c
4 files changed, 7 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/32608/1

diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c
index 9f919cf..2a764aa 100644
--- a/src/northbridge/intel/gm45/early_reset.c
+++ b/src/northbridge/intel/gm45/early_reset.c
@@ -16,6 +16,7 @@

#include <types.h>
 #include <arch/io.h>
+#include <cf9_reset.h>
 #include <device/pci_ops.h>
 #include <halt.h>
 #include "gm45.h"
@@ -65,6 +66,5 @@

/* Perform system reset through CF9 interface. */
    outb(0x02, 0xcf9); /* Set system reset bit. */
-	outb(0x06, 0xcf9); /* Set CPU reset bit, too. */
-	halt();
+	system_reset(); /* Set CPU reset bit, too. */
 }
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c
index 48bca36..4e7e03f 100644
--- a/src/northbridge/intel/pineview/raminit.c
+++ b/src/northbridge/intel/pineview/raminit.c
@@ -15,6 +15,7 @@
  */

#include <arch/io.h>
+#include <cf9_reset.h>
 #include <device/mmio.h>
 #include <device/pci_ops.h>
 #include <console/console.h>
@@ -1746,7 +1747,7 @@
    pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, pmcon3);
    if (reset) {
    	printk(BIOS_DEBUG, "Power cycle reset...\n");
-		outb(0xe, 0xcf9);
+		full_reset();
    }
 }

diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index 3fab3be..781b9ac 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -18,6 +18,7 @@
 #include <stdint.h>
 #include <console/console.h>
 #include <arch/io.h>
+#include <cf9_reset.h>
 #include <device/pci_ops.h>
 #include <cpu/x86/lapic.h>
 #include <timestamp.h>
@@ -48,8 +49,7 @@
    int s3resume = 0;

if (MCHBAR16(SSKPD) == 0xCAFE) {
-		outb(0x6, 0xcf9);
-		halt ();
+		system_reset();
    }

if (bist == 0)
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 4d5bdce..6dc2e5f 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -625,8 +625,7 @@
    	pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 |  (1 << 2));

printk(BIOS_DEBUG, "Reset...\n");
-		outb(0xe, 0xcf9);
-		asm ("hlt");
+		full_reset();
    }
    pmcon2 |= 0x80;
    pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2);