[coreboot-gerrit] Change in coreboot[master]: siemens/mc_apl1: Make the DDR memory swizzle data configurable

[Mario Scheithauer (Code Review)]

Hello Werner Zeh, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/28730

to look at the new patch set (#2).

Change subject: siemens/mc_apl1: Make the DDR memory swizzle data configurable
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siemens/mc_apl1: Make the DDR memory swizzle data configurable

In preparation for a future MC Apollo Lake board which will be equipped
with LPDDR4 modules, it is necessary to make the swizzle data
configurable. Starting from the mc_apl1 baseboard, which is equipped
with DDR3L memory and therefore does not need swizzle data, the
structures are initialized with zero.

Change-Id: I4954d0a00d1d5fc28a8dda45a9fb27f98d5c3f1e
Signed-off-by: Mario Scheithauer 
---
M src/mainboard/siemens/mc_apl1/romstage.c
M src/mainboard/siemens/mc_apl1/variants/baseboard/Makefile.inc
M src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h
A src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c
4 files changed, 142 insertions(+), 34 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/28730/2