[coreboot-gerrit] Change in coreboot[master]: AGESA,binaryPI: Split romstage_main() to BSP and AP parts

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37326 )

Change subject: AGESA,binaryPI: Split romstage_main() to BSP and AP parts
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AGESA,binaryPI: Split romstage_main() to BSP and AP parts

BSP and AP have two distinct execution paths for romstage.

Change-Id: Id013b165f1345509fe6b74cef2bf8c3b420f84a4
Signed-off-by: Kyösti Mälkki 
---
M src/drivers/amd/agesa/romstage.c
M src/include/cpu/amd/car.h
2 files changed, 29 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/37326/1

diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c
index 0ecfeb2..5a40ba8 100644
--- a/src/drivers/amd/agesa/romstage.c
+++ b/src/drivers/amd/agesa/romstage.c
@@ -40,7 +40,7 @@
    agesa_set_interface(cb);
 }

-void *asmlinkage romstage_main(unsigned long bist)
+static void bsp_romstage_main(unsigned long bist)
 {
    struct postcar_frame pcf;
    struct sysinfo romstage_state;
@@ -53,7 +53,7 @@

fill_sysinfo(cb);

-	if ((initial_apic_id == 0) && boot_cpu()) {
+	if (initial_apic_id == 0) {

timestamp_init(timestamp_get());
    	timestamp_add_now(TS_START_ROMSTAGE);
@@ -101,5 +101,30 @@

run_postcar_phase(&pcf);
    /* We do not return. */
-	return NULL;
+}
+
+static void __noreturn ap_romstage_main(void)
+{
+	struct sysinfo romstage_state;
+	struct sysinfo *cb = &romstage_state;
+
+	/* Enable PCI MMIO configuration. */
+	amd_initmmio();
+
+	fill_sysinfo(cb);
+
+	agesa_execute_state(cb, AMD_INIT_RESET);
+
+	agesa_execute_state(cb, AMD_INIT_EARLY);
+
+	/* Not reached. */
+	halt();
+}
+
+void asmlinkage romstage_main(unsigned long bist)
+{
+	if (boot_cpu())
+		bsp_romstage_main(bist);
+	else
+		ap_romstage_main();
 }
diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h
index 46f7e1d..61c2388 100644
--- a/src/include/cpu/amd/car.h
+++ b/src/include/cpu/amd/car.h
@@ -5,6 +5,6 @@

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);

-void *asmlinkage romstage_main(unsigned long bist);
+void asmlinkage romstage_main(unsigned long bist);

#endif