[coreboot-gerrit] [M] Change in coreboot[master]: [DONOTMERGE] soc/intel/alderlake: Add panel support

[Jérémy Compostella (Code Review)]

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69754 )

Change subject: [DONOTMERGE] soc/intel/alderlake: Add panel support
......................................................................

[DONOTMERGE] soc/intel/alderlake: Add panel support

Signed-off-by: Jeremy Compostella 
Change-Id: I44d957ff902c60f1d3281a05a618a5d89ace8022
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/graphics.c
3 files changed, 80 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/69754/1

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 08d4132..abd0570 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -45,6 +45,11 @@

config CPU_SPECIFIC_OPTIONS
    def_bool y
+	select ENABLE_TCSS_DISPLAY_DETECTION
+	select MAINBOARD_HAS_LIBGFXINIT
+	select MAINBOARD_USE_LIBGFXINIT
+	select VGA_TEXT_FRAMEBUFFER
+	select GFX_GMA
    select ACPI_INTEL_HARDWARE_SLEEP_VALUES
    select ACPI_ADL_IPU_ES_SUPPORT
    select ARCH_X86
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index a732fe6..c9d713f 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -6,6 +6,7 @@
 #include <drivers/i2c/designware/dw_i2c.h>
 #include <drivers/intel/gma/gma.h>
 #include <device/pci_ids.h>
+#include <drivers/intel/gma/gma.h>
 #include <intelblocks/cfg.h>
 #include <intelblocks/gpio.h>
 #include <intelblocks/gspi.h>
@@ -256,6 +257,17 @@
    /* Common struct containing power limits configuration information */
    struct soc_power_limits_config power_limits_config[ADL_POWER_LIMITS_COUNT];

+	/*
+	 * IGD panel configuration
+	 *
+	 * Second backlight control shares logic with other pins (aka. display utility pin).
+	 * Be sure it's used for PWM before setting any secondary backlight value.
+	 */
+	struct i915_gpu_panel_config panel_cfg;
+
+	/* i915 struct for GMA backlight control */
+	struct i915_gpu_controller_info gfx;
+
    /* Gpio group routed to each dword of the GPE0 block. Values are
     * of the form PMC_GPP_[A:U] or GPD. */
    uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */
diff --git a/src/soc/intel/alderlake/graphics.c b/src/soc/intel/alderlake/graphics.c
index f2c792c..41d9d7c 100644
--- a/src/soc/intel/alderlake/graphics.c
+++ b/src/soc/intel/alderlake/graphics.c
@@ -1,7 +1,60 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */

+#include <commonlib/helpers.h>
+#include <device/device.h>
+#include <device/mmio.h>
+#include <device/pci_def.h>
+#include <device/resource.h>
+#include <drivers/intel/gma/i915_reg.h>
 #include <intelblocks/graphics.h>
 #include <soc/ramstage.h>
+#include <types.h>
+
+void graphics_soc_panel_init(struct device *dev)
+{
+	const struct soc_intel_alderlake_config *conf = dev->chip_info;
+	const struct i915_gpu_panel_config *panel_cfg;
+	const struct resource *mmio_res;
+	void *mmio;
+	uint32_t reg32;
+	unsigned int pwm_period, pwm_polarity, pwm_duty;
+
+	if (!conf)
+		return;
+
+	panel_cfg = &conf->panel_cfg;
+
+	mmio_res = probe_resource(dev, PCI_BASE_ADDRESS_0);
+	if (!mmio_res || !mmio_res->base)
+		return;
+	mmio = (void *)(uintptr_t)mmio_res->base;
+
+	/* Panel timings */
+
+	reg32 = ((DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f) << 4;
+	reg32 |= PANEL_POWER_RESET;
+	write32(mmio + PCH_PP_CONTROL, reg32);
+
+	reg32 = ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16;
+	reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff;
+	write32(mmio + PCH_PP_ON_DELAYS, reg32);
+
+	reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16;
+	reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff;
+	write32(mmio + PCH_PP_OFF_DELAYS, reg32);
+
+	/* Backlight */
+	if (panel_cfg->backlight_pwm_hz) {
+		printk(BIOS_DEBUG, "J2M: Initalizing backlight\n");
+		pwm_polarity = panel_cfg->backlight_polarity ? BXT_BLC_PWM_POLARITY : 0;
+		pwm_period = DIV_ROUND_CLOSEST(CONFIG_CPU_XTAL_HZ, panel_cfg->backlight_pwm_hz);
+		pwm_duty = DIV_ROUND_CLOSEST(pwm_period, 2); /* Start with 50 % */
+
+		write32(mmio + BXT_BLC_PWM_FREQ(0), pwm_period);
+		write32(mmio + BXT_BLC_PWM_CTL(0),  pwm_polarity);
+		write32(mmio + BXT_BLC_PWM_DUTY(0), pwm_duty);
+	}
+}

const struct i915_gpu_controller_info *
 intel_igd_get_controller_info(const struct device *const dev)