Hello Kyösti Mälkki, Werner Zeh, David Hendricks, Aaron Durbin, Angel Pons, Arthur Heymans, Patrick Rudolph, Stefan Reinauer, Philip Prindeville, Patrick Georgi,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/34282
to review the following change.
Change subject: Revert "soc/intel/cannonlake: Add option to select FSP_CAR" ......................................................................
Revert "soc/intel/cannonlake: Add option to select FSP_CAR"
This reverts commit 9e3ba212f34c6d9f2eb7dac8e4651f8ce12ab0c0.
It rudely changed the default CAR implementation from open-source to the proprietary FSP-T. That it was reviewed by Google and contains a safeguard so that it doesn't affect Google reeks of corporate arrogance. My attempts to find a civilized solution failed, because the author is blocking any progress.
Change-Id: Ief7b85a9988d1a3f4a4639e9fd304959295958bd --- M src/soc/intel/cannonlake/Kconfig 1 file changed, 2 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/34282/1
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index fed7f02..f30ff11 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -68,6 +68,7 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE + select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC @@ -86,6 +87,7 @@ select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT @@ -267,33 +269,6 @@ This will enable a workaround in ASL _PS3 and _PS0 methods to force SD_PWR_ENABLE to stay low in D3.
-choice - prompt "Cache-as-ram implementation" - default USE_CANNONLAKE_CAR_NEM_ENHANCED if MAINBOARD_HAS_CHROMEOS - default USE_CANNONLAKE_FSP_CAR - help - This option allows you to select how cache-as-ram (CAR) is set up. - -config USE_CANNONLAKE_CAR_NEM_ENHANCED - bool "Enhanced Non-evict mode" - select SOC_INTEL_COMMON_BLOCK_CAR - select INTEL_CAR_NEM_ENHANCED - help - A current limitation of NEM (Non-Evict mode) is that code and data - sizes are derived from the requirement to not write out any modified - cache line. With NEM, if there is no physical memory behind the - cached area, the modified data will be lost and NEM results will be - inconsistent. ENHANCED NEM guarantees that modified data is always - kept in cache while clean data is replaced. - -config USE_CANNONLAKE_FSP_CAR - bool "Use FSP CAR" - select FSP_CAR - help - Use FSP APIs to initialize and tear down the Cache-As-Ram. - -endchoice - config FSP_HEADER_PATH string "Location of FSP headers" default "3rdparty/fsp/CoffeeLakeFspBinPkg/Include/" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE