Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38623 )
Change subject: hatch/mushu: Fix FPMCU pwr/rst gpio handling ......................................................................
hatch/mushu: Fix FPMCU pwr/rst gpio handling
Asserting reset in RO instead of in RW has no impact on security or performance, but it does limit improvements to this process later. This fix removes reset line control from RO and makes these variants consistent with other hatch variants.
This fix reinforces the concept from commit fcd8c9e99e (hatch: Fix FPMCU pwr/rst gpio handling).
BUG=b:148457345 TEST=None
Change-Id: I12dc0c3bead7672e2d3207771212efb0d246973a Signed-off-by: Craig Hesling hesling@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/38623 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net --- M src/mainboard/google/hatch/variants/hatch/Makefile.inc M src/mainboard/google/hatch/variants/hatch/gpio.c A src/mainboard/google/hatch/variants/hatch/ramstage.c M src/mainboard/google/hatch/variants/mushu/Makefile.inc M src/mainboard/google/hatch/variants/mushu/gpio.c A src/mainboard/google/hatch/variants/mushu/ramstage.c 6 files changed, 56 insertions(+), 6 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/variants/hatch/Makefile.inc b/src/mainboard/google/hatch/variants/hatch/Makefile.inc index a990b5a..4bf640a 100644 --- a/src/mainboard/google/hatch/variants/hatch/Makefile.inc +++ b/src/mainboard/google/hatch/variants/hatch/Makefile.inc @@ -19,5 +19,7 @@ SPD_SOURCES += 16G_2400 # 0b100 SPD_SOURCES += 16G_2666 # 0b101
-ramstage-y += gpio.c bootblock-y += gpio.c + +ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/hatch/variants/hatch/gpio.c b/src/mainboard/google/hatch/variants/hatch/gpio.c index 862b28f..2c4fa50 100644 --- a/src/mainboard/google/hatch/variants/hatch/gpio.c +++ b/src/mainboard/google/hatch/variants/hatch/gpio.c @@ -55,8 +55,6 @@ * needed in this table. */ static const struct pad_config early_gpio_table[] = { - /* A12 : FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_A12, 0, DEEP), /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : H1_SLAVE_SPI_CLK */ diff --git a/src/mainboard/google/hatch/variants/hatch/ramstage.c b/src/mainboard/google/hatch/variants/hatch/ramstage.c new file mode 100644 index 0000000..5459f55 --- /dev/null +++ b/src/mainboard/google/hatch/variants/hatch/ramstage.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_ramstage_init(void) +{ + /* + * Enable power to FPMCU, wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while, + * a minimum of 400us on Kohaku. + */ + gpio_output(GPP_C11, 1); + mdelay(1); + gpio_output(GPP_A12, 1); +} diff --git a/src/mainboard/google/hatch/variants/mushu/Makefile.inc b/src/mainboard/google/hatch/variants/mushu/Makefile.inc index a990b5a..4bf640a 100644 --- a/src/mainboard/google/hatch/variants/mushu/Makefile.inc +++ b/src/mainboard/google/hatch/variants/mushu/Makefile.inc @@ -19,5 +19,7 @@ SPD_SOURCES += 16G_2400 # 0b100 SPD_SOURCES += 16G_2666 # 0b101
-ramstage-y += gpio.c bootblock-y += gpio.c + +ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/hatch/variants/mushu/gpio.c index a60662a..fd12eb0 100644 --- a/src/mainboard/google/hatch/variants/mushu/gpio.c +++ b/src/mainboard/google/hatch/variants/mushu/gpio.c @@ -59,8 +59,6 @@ * needed in this table. */ static const struct pad_config early_gpio_table[] = { - /* A12 : FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_A12, 0, DEEP), /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : H1_SLAVE_SPI_CLK */ diff --git a/src/mainboard/google/hatch/variants/mushu/ramstage.c b/src/mainboard/google/hatch/variants/mushu/ramstage.c new file mode 100644 index 0000000..5459f55 --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/ramstage.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_ramstage_init(void) +{ + /* + * Enable power to FPMCU, wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while, + * a minimum of 400us on Kohaku. + */ + gpio_output(GPP_C11, 1); + mdelay(1); + gpio_output(GPP_A12, 1); +}