Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45087 )
Change subject: soc/intel/tigerlake: Add config option to enable TME ......................................................................
soc/intel/tigerlake: Add config option to enable TME
Add config option to set TmeEnable FSP-M upd. The TME spec is available at: "https://software.intel.com/sites/ default/files/managed/a5/16/Multi-Key-Total-Memory-Encryption- Spec.pdf"
Test: TME ENABLE and LOCK bits get set when Tme is enabled.
Signed-off-by: Pratik Prajapati pratikkumar.v.prajapati@intel.com Change-Id: I181aed2bf4a79005fe42e3e133b5faee91201dad --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/romstage/fsp_params.c 2 files changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/45087/1
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 8718f97..42f83ee 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -215,4 +215,12 @@ config PRERAM_CBMEM_CONSOLE_SIZE hex default 0x1400 + +config INTEL_TME + bool "Total Memory Encryption (TME)" + default n + help + Enable Total Memory Encryption (TME). The spec is available at + "https://software.intel.com/sites/default/files/managed/a5/16/Multi- + Key-Total-Memory-Encryption-Spec.pdf". endif diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 2ba276d..4e47959 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -208,6 +208,9 @@ /* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */ dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE); m_cfg->CpuPcieRpEnableMask = dev && dev->enabled; + + /* Change TmeEnable UPD value according to ENABLE_TME Kconfig */ + m_cfg->TmeEnable = CONFIG(INTEL_TME); }
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)