Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48564 )
Change subject: soc/amd/cezanne: add GPIO definitions ......................................................................
Patch Set 2:
(4 comments)
https://review.coreboot.org/c/coreboot/+/48564/1/src/soc/amd/cezanne/include... File src/soc/amd/cezanne/include/soc/gpio.h:
https://review.coreboot.org/c/coreboot/+/48564/1/src/soc/amd/cezanne/include... PS1, Line 251: #define GPIO_140_IOMUX_GPIOxx 0 : #define GPIO_140_IOMUX_UART0_CTS_L 1
I just had a look at the revision 3.06 of the Renoir PPR and it matches both revision 3. […]
Done. Yes. I downloaded the 3.06 and found some GPIO definitions has changed.
https://review.coreboot.org/c/coreboot/+/48564/1/src/soc/amd/cezanne/include... PS1, Line 255: #define GPIO_141_IOMUX_GPIOxx 0 : #define GPIO_141_IOMUX_UART0_RXD 1
For RN, same as 140.
Done
https://review.coreboot.org/c/coreboot/+/48564/1/src/soc/amd/cezanne/include... PS1, Line 258: #define GPIO_142_IOMUX_GPIOxx 0 : #define GPIO_142_IOMUX_UART0_RTS_L 1 : #define GPIO_142_IOMUX_UART1_RXD 2 : #define GPIO_142_IOMUX_SD0_DATA0 3
For RN, […]
Done
https://review.coreboot.org/c/coreboot/+/48564/1/src/soc/amd/cezanne/include... PS1, Line 265: #define GPIO_144_IOMUX_GPIOxx 0 : #define GPIO_144_IOMUX_UART0_INTR 2
For RN, switch.
Done