[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/{skylake,cannonlake,icelake}: Correct GPIO IRQ start map

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31245

Change subject: soc/intel/{skylake,cannonlake,icelake}: Correct GPIO IRQ start map
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soc/intel/{skylake,cannonlake,icelake}: Correct GPIO IRQ start map

This implementation corrects the GPIO IRQ start map used for ITSS
polarity configuration. The lowest GPIO IRQ mapped in SKL/KBL, CNL,
and ICL is 24.

BUG=b:123315212
TEST=[TESTED on CNL-ONLY]
     Verify the ITSS polarity configuration for GPIOs are correctly
     getting restored to original coreboot configuration, after fsp-s
     call in itss_restore_irq_polarities() call.

Change-Id: I3c12e6ca01453da92259f077771c3f4d887aa03d
Signed-off-by: Aamir Bohra 
---
M src/soc/intel/cannonlake/include/soc/itss.h
M src/soc/intel/icelake/include/soc/itss.h
M src/soc/intel/skylake/include/soc/itss.h
3 files changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/31245/1

diff --git a/src/soc/intel/cannonlake/include/soc/itss.h b/src/soc/intel/cannonlake/include/soc/itss.h
index 0d8b2ca..09245e7 100644
--- a/src/soc/intel/cannonlake/include/soc/itss.h
+++ b/src/soc/intel/cannonlake/include/soc/itss.h
@@ -16,7 +16,7 @@
 #ifndef SOC_INTEL_CNL_ITSS_H
 #define SOC_INTEL_CNL_ITSS_H

-#define GPIO_IRQ_START	50
+#define GPIO_IRQ_START	24
 #define GPIO_IRQ_END	ITSS_MAX_IRQ

#define ITSS_MAX_IRQ	119
diff --git a/src/soc/intel/icelake/include/soc/itss.h b/src/soc/intel/icelake/include/soc/itss.h
index d846ce0..c27a2ea 100644
--- a/src/soc/intel/icelake/include/soc/itss.h
+++ b/src/soc/intel/icelake/include/soc/itss.h
@@ -16,7 +16,7 @@
 #ifndef SOC_INTEL_ICL_ITSS_H
 #define SOC_INTEL_ICL_ITSS_H

-#define GPIO_IRQ_START	50
+#define GPIO_IRQ_START	24
 #define GPIO_IRQ_END	ITSS_MAX_IRQ

#define ITSS_MAX_IRQ	119
diff --git a/src/soc/intel/skylake/include/soc/itss.h b/src/soc/intel/skylake/include/soc/itss.h
index e6eb8b0..a987cab 100644
--- a/src/soc/intel/skylake/include/soc/itss.h
+++ b/src/soc/intel/skylake/include/soc/itss.h
@@ -16,7 +16,7 @@
 #ifndef SOC_INTEL_SKL_ITSS_H
 #define SOC_INTEL_SKL_ITSS_H

-#define GPIO_IRQ_START	50
+#define GPIO_IRQ_START	24
 #define GPIO_IRQ_END	ITSS_MAX_IRQ

#define ITSS_MAX_IRQ	119