Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31477 )
Change subject: riscv: workaround selfboot putting the coreboot table into prog_entry_arg
......................................................................
Patch Set 10:
Patch Set 10:
@Xiang: Please change the following in the RISC-V documentation as well:
-On entry to a stage or payload,
+On entry to a stage or payload (including SELF payloads),
Updated! Please refer https://review.coreboot.org/c/coreboot/+/33460
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