[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Configure voltage margining policies

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32026 )

Change subject: soc/intel/cannonlake: Configure voltage margining policies
......................................................................

soc/intel/cannonlake: Configure voltage margining policies

For systems that integrate GbE controllers, following parameters should be configured:
SlpS0WithGbeSupport: enable PchPmSlpS0VmRuntimeControl: disable,
PchPmSlpS0Vm070VSupport: disable, PchPmSlpS0Vm075VSupport: disable.

TEST=boot on any GbE supported WHL platform

Change-Id: I02aaf0b77b8fc1555a3a424c02acfada21707d0e
Signed-off-by: Krzysztof Sywula 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32026
Tested-by: build bot (Jenkins) 
Reviewed-by: Duncan Laurie 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 17 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Duncan Laurie: Looks good to me, approved

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 5d9c744..a81a7c1 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -138,6 +138,15 @@
    uint8_t SataPortsEnable[8];
    uint8_t SataPortsDevSlp[8];

+	/* Enable/Disable SLP_S0 with GBE Support. 0: disable, 1: enable */
+	uint8_t SlpS0WithGbeSupport;
+	/* SLP_S0 Voltage Margining Policy. 0: disable, 1: enable */
+	uint8_t PchPmSlpS0VmRuntimeControl;
+	/* SLP_S0 Voltage Margining  0.70V Policy. 0: disable, 1: enable */
+	uint8_t PchPmSlpS0Vm070VSupport;
+	/* SLP_S0 Voltage Margining  0.75V Policy. 0: disable, 1: enable */
+	uint8_t PchPmSlpS0Vm075VSupport;
+
    /* Audio related */
    uint8_t PchHdaDspEnable;

diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 1a3b4fb..6173403 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -161,8 +161,15 @@
    dev = dev_find_slot(0, PCH_DEVFN_GBE);
    if (!dev)
    	params->PchLanEnable = 0;
-	else
+	else {
    	params->PchLanEnable = dev->enabled;
+		if (config->s0ix_enable) {
+			params->SlpS0WithGbeSupport = 1;
+			params->PchPmSlpS0VmRuntimeControl = 0;
+			params->PchPmSlpS0Vm070VSupport = 0;
+			params->PchPmSlpS0Vm075VSupport = 0;
+		}
+	}

/* Audio */
    params->PchHdaDspEnable = config->PchHdaDspEnable;