17 Aug
2021
17 Aug
'21
8:16 a.m.
Attention is currently required from: Felix Singer, Bora Guvendik, Lijian Zhao, Shaunak Saha, Nico Huber, Furquan Shaikh, Martin Roth, Michael Niewöhner, Tim Wawrzynczak, Vaibhav Shankar, Aaron Durbin, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56662 )
Change subject: Revert "src/soc/intel/cannonlake: Update C-state latency control limits" ......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56662/comment/4deb9b97_aa2225ff PS1, Line 14:
Alas, I don't have the hardware to confirm the S0ix status.
Michael, did you ever manage to achieve S0ix on your CML-U device?
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iea56c6a29ca4b34c9852393fed2e3be4de128ec6
Gerrit-Change-Number: 56662
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Singer felixsinger@posteo.net
Gerrit-Reviewer: Aaron Durbin adurbin@chromium.org
Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com
Gerrit-Reviewer: Bora Guvendik bora.guvendik@intel.com
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