Attention is currently required from: Benjamin Doron, Patrick Rudolph. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50724 )
Change subject: [DNM] soc/intel: Fix SPI write protect and EISS support ......................................................................
Patch Set 3:
(2 comments)
File src/soc/intel/common/block/fast_spi/fast_spi.c:
https://review.coreboot.org/c/coreboot/+/50724/comment/2a7d5cab_fa7664f2 PS3, Line 55: /* Skip on S3 resume, in bootblock, with SPI lockdown configured? this condition is wrong. bios should always try to unlock and enable write support. When in bootblock all registers are unlocked.
File src/soc/intel/common/block/smm/smihandler.c:
https://review.coreboot.org/c/coreboot/+/50724/comment/316fdd11_5aa5988f PS3, Line 58: /* FIXME: TCO1_STS "BIOSWR_STS" bit is only set for LPC on eSPI/SPI only a TCO SMI is generated. Manually checking the registers for WPD is correct.