[coreboot-gerrit] Change in ...coreboot[master]: HACK: Julius' hack for v20

[Julius Werner (Code Review)]

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30941

Change subject: HACK: Julius' hack for v20
......................................................................

HACK: Julius' hack for v20

This is a quick hack to get us 8GB support while the actual QcLib fix is
still in the pipeline.

Change-Id: I255b22f16242274f68698283cb0fab1a1550f7e8
Signed-off-by: Julius Werner 
---
M src/soc/qualcomm/sdm845/qclib_execute.c
1 file changed, 19 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/30941/1

diff --git a/src/soc/qualcomm/sdm845/qclib_execute.c b/src/soc/qualcomm/sdm845/qclib_execute.c
index f71daa8..7ddf8e6 100644
--- a/src/soc/qualcomm/sdm845/qclib_execute.c
+++ b/src/soc/qualcomm/sdm845/qclib_execute.c
@@ -83,6 +83,7 @@

static void write_ddr_information(struct qclib_cb_if_table_entry *te)
 {
+return;
    uint64_t ddr_size;

/* Save DDR info in SRAM region to share with ramstage */
@@ -99,9 +100,26 @@
 {
    int i;
    char *ptr = (char *)te->blob_address;
+	const char pattern[] = "Rank 1 size = ";
+	const char size4gb[] = "4096 MB";

-	for (i = 0; i < te->size; i++)
+	ddr_region->offset = (uintptr_t)_dram;
+	ddr_region->size = 4UL*GiB;
+
+	for (i = 0; i < te->size; i++) {
    	cbmemc_tx_byte(*ptr++);
+		if (te->size - i > sizeof(pattern) &&
+		    !strncmp(ptr, pattern, sizeof(pattern) - 1)) {
+			char *rank1_mb = ptr + sizeof(pattern) - 1;
+			if (!strncmp(rank1_mb, size4gb, sizeof(size4gb) - 1)) {
+				printk(BIOS_DEBUG, "JWERNER: 8GB Cheza!\n");
+				ddr_region->size = 8UL*GiB;
+			}
+		}
+	}
+
+	sdm845_mmu_dram_config_post_dram_init((void *)ddr_region->offset,
+		(size_t)ddr_region->size);
 }

static void write_table_entry(struct qclib_cb_if_table_entry *te)