[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Fix overlapping memory address used for early GS...

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47643 )

Change subject: soc/intel/tigerlake: Fix overlapping memory address used for early GSPI2 and UART bars
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Patch Set 1: Code-Review+2

(1 comment)

https://review.coreboot.org/c/coreboot/+/47643/1/src/soc/intel/tigerlake/Kco... 
File src/soc/intel/tigerlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/47643/1/src/soc/intel/tigerlake/Kco... 
PS1, Line 169: 0xfe03e000
I don't understand why we have the BAR defined in two different places: https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/tigerlake/i...

Probably because it gets used by the payload as well. We might want to evaluate if there is a way to pass the address to the payload instead of using coreboot configs. Anyways, that would be for a separate change.