[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Use CS0 for GSPI0 in FSP parameters.

[Aaron Durbin (Code Review)]

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32791 )

Change subject: soc/intel/cannonlake: Use CS0 for GSPI0 in FSP parameters.
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Patch Set 3:

(1 comment)

https://review.coreboot.org/#/c/32791/3/src/soc/intel/cannonlake/fsp_params.... 
File src/soc/intel/cannonlake/fsp_params.c:

https://review.coreboot.org/#/c/32791/3/src/soc/intel/cannonlake/fsp_params.... 
PS3, Line 369: 		params->SerialIoSpi0CsEnable[0] = 1;
You shouldn't bake in board specific attributes in non-board specific places. This is the soc directory and should work for all uses of the SoC.