[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake/bootblock: Clear the GPI IS & IE registers

[Furquan Shaikh (Code Review)]

Furquan Shaikh has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34624 )

Change subject: soc/intel/cannonlake/bootblock: Clear the GPI IS & IE registers
......................................................................

soc/intel/cannonlake/bootblock: Clear the GPI IS & IE registers

Clear the GPI Interrupt Status & Enable registers to prevent any
interrupt storms due to GPI.

BUG=b:138282962
TEST=Ensure that the Interrupt status & enable registers are reset
during the boot-up when the system is brought out of G3, S5 & S3. Ensure
that the system boots fine to ChromeOS.

Change-Id: I2185355d0095601e0778b6bf47ae137cc53e4051
Signed-off-by: David Wu 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34624
Tested-by: build bot (Jenkins) 
Reviewed-by: Karthik Ramasubramanian 
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Paul Fagerburg 
---
M src/soc/intel/cannonlake/bootblock/bootblock.c
1 file changed, 5 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Karthik Ramasubramanian: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved
  Paul Fagerburg: Looks good to me, approved

diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c
index 5555969..30c2266 100644
--- a/src/soc/intel/cannonlake/bootblock/bootblock.c
+++ b/src/soc/intel/cannonlake/bootblock/bootblock.c
@@ -59,6 +59,11 @@

void bootblock_soc_init(void)
 {
+	/*
+	 * Clear the GPI interrupt status and enable registers. These
+	 * registers do not get reset to default state when booting from S5.
+	 */
+	gpi_clear_int_cfg();
    report_platform_info();
    pch_early_init();
 }