huayang duan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32243 )
Change subject: mediatek/mt8183: support SAMSUNG and MICRON EMCP LPDDR4X DDR bootup ......................................................................
Patch Set 6:
(8 comments)
https://review.coreboot.org/#/c/32243/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32243/4//COMMIT_MSG@9 PS4, Line 9: support
Support
Done
https://review.coreboot.org/#/c/32243/4//COMMIT_MSG@10 PS4, Line 10: supprot
Support
Done
https://review.coreboot.org/#/c/32243/4//COMMIT_MSG@12 PS4, Line 12: from
From
Done
https://review.coreboot.org/#/c/32243/4//COMMIT_MSG@13 PS4, Line 13: early
earlier
Done
https://review.coreboot.org/#/c/32243/4//COMMIT_MSG@13 PS4, Line 13: than other
than with other
Done
https://review.coreboot.org/#/c/32243/4//COMMIT_MSG@12 PS4, Line 12: from the calibration log of MICRON MT29VZZZAD8DQKSL, we found : the begin pass range of RX window early than other DDR type.
Why is that a bad thing? Is that contradicting some specification?
The delay begin is just used to scan the QQ to QDS window, not relate with bad thing. For normal case, we should put the delay begin to very very left side and do window scan to found the left pass window. Then delay+1 do window scan again, repeat do those step to found all pass window. The value of very very left side should be -63 for first bring-up, because it can cover all case. But it will spend more time to scan QQ to QDS window. after bring-up success, we will analyze the QQ to QDS window scan UART logs, decrease the unused scan to reduce the bootup time, so we change the delay begin from -63 to -10. But From the calibration log of EMCP-SAMSUNG DDR, we found the begin pass range of RX window early than other DDR. Because the pass window will be affected by SOC chip manufacturing process, DDR chip manufacturing process, current volatge, temperature and some other environment. If we not increase the begin scan range, the pass window maybe get wrong result at some board.
https://review.coreboot.org/#/c/32243/4//COMMIT_MSG@13 PS4, Line 13: begin
start of
we prefer using begin for DRAM calibration flow
https://review.coreboot.org/#/c/32243/4//COMMIT_MSG@14 PS4, Line 14: change
Change
Done