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I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/58811
to review the following change.
Change subject: Revert "soc/intel/adl: Drop SGPM, RGPM and EGPM methods" ......................................................................
Revert "soc/intel/adl: Drop SGPM, RGPM and EGPM methods"
This reverts commit 1399442289607acc5203fb12df64e9081b3c3aa4.
Reason for revert: Some Cr50 chips with old firmware version(x.y.22) doesn't support long pulse interrupt command, requires dynamic GPIO PM to be disabled to intercept short pulse interrupt.
Due to this coreboot needs to expose SGPM, RGPM and EGPM ACPI methods to support power gating of GPIO communities from the kernel when dynamic GPIO PM is disabled.
Change-Id: I2b5b00878062f8a499641d7a47db54ed078cd6cf --- M src/soc/intel/alderlake/acpi/gpio.asl 1 file changed, 41 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/58811/1
diff --git a/src/soc/intel/alderlake/acpi/gpio.asl b/src/soc/intel/alderlake/acpi/gpio.asl index 6a1ba00..376afab 100644 --- a/src/soc/intel/alderlake/acpi/gpio.asl +++ b/src/soc/intel/alderlake/acpi/gpio.asl @@ -137,3 +137,44 @@
Return (Local0) } + +/* GPIO Power Management bits */ +Name(GPMB, Package(TOTAL_GPIO_COMM) {0, 0, 0, 0, 0, 0}) + +/* + * Save GPIO Power Management bits + */ +Method (SGPM, 0, Serialized) +{ + For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++) + { + Local1 = GPID (Local0) + GPMB[Local0] = PCRR (Local1, GPIO_MISCCFG) + } +} + +/* + * Restore GPIO Power Management bits + */ +Method (RGPM, 0, Serialized) +{ + For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++) + { + CGPM (Local0, DerefOf(GPMB[Local0])) + } +} + +/* + * Save current setting of GPIO Power Management bits and + * enable all Power Management bits for all communities + */ +Method (EGPM, 0, Serialized) +{ + /* Save current setting and will restore it when resuming */ + SGPM () + /* Enable PM bits */ + For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++) + { + CGPM (Local0, MISCCFG_GPIO_PM_CONFIG_BITS) + } +}