Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29772
Change subject: soc/intel/apollolake: Add Kconfig switch to enable max efficiency clock ......................................................................
soc/intel/apollolake: Add Kconfig switch to enable max efficiency clock
Add a Kconfig switch to be able to set the CPU clock to maximum efficiency mode. If enabled the CPU will be clocked with the lowest possible frequency while consuming as little power as possible.
Change-Id: I4a59586da72d1915749110a36f565fe2aa69e073 Signed-off-by: Werner Zeh werner.zeh@siemens.com --- M src/soc/intel/apollolake/Kconfig 1 file changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/29772/1
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 0c0fca9..336847a 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -370,12 +370,23 @@
config APL_SKIP_SET_POWER_LIMITS bool + depends on !APL_SET_MAX_EFFICIENCY_MODE default n help Some Apollo Lake mainboards do not need the Running Average Power Limits (RAPL) algorithm for a constant power management. Set this config option to skip the RAPL configuration.
+config APL_SET_MAX_EFFICIENCY_MODE + bool + depends on !APL_SKIP_SET_POWER_LIMITS + default n + help + If the power budget of the mainboard is limited, it can be useful to + limit the CPU power dissipation at the cost of performance by setting + the lowest possible CPU clock. Enable this option if you need maximum + CPU efficiency. + # M and N divisor values for clock frequency configuration. # These values get us a 1.836 MHz clock (ideally we want 1.843 MHz) config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL