[coreboot-gerrit] Change in coreboot[master]: nb/intel/sandybridge/early_init: Read Gen3 feature disable fuse

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/20928

Change subject: nb/intel/sandybridge/early_init: Read Gen3 feature disable fuse
......................................................................

nb/intel/sandybridge/early_init: Read Gen3 feature disable fuse

Read the PCIe Gen3 feature disable fuse and set PCIe target link speed
accordingly. This feature is likely used on mobile platforms.

Needs tests on all platforms.

Change-Id: Id08f7e52064ae8b550a122b35d918d6d97193b13
Signed-off-by: Patrick Rudolph 
---
M src/northbridge/intel/sandybridge/early_init.c
1 file changed, 26 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/20928/1

diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index f014e80..a5c6ce2 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -272,6 +272,7 @@
 {
    u32 tmp;
    u32 deven;
+	u32 link_mask = (7 << 1);

/* PEG on IvyBridge+ needs a special startup sequence.
     * As the MRC has its own initialization code skip it. */
@@ -280,22 +281,47 @@
    	IS_ENABLED(CONFIG_HAVE_MRC))
    	return;

+	/* Read PEG10 Gen3 feature disable fuse */
+	if (pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_B) & (1 << 20)) {
+		printk(BIOS_DEBUG, "PEG: PCIe Gen3 disabled\n");
+		link_mask = (3 << 1);
+	} else
+		printk(BIOS_DEBUG, "PEG: PCIe Gen3 supported\n");
+
    /* Configure PEG10/PEG11/PEG12 PHY */
    ivybridge_peg_phy();

deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN);

if (deven & DEVEN_PEG10) {
+		/* Update PEG10 target link speed */
+		tmp = pci_read_config32(PCI_DEV(0, 1, 0), LCAP2);
+		tmp &= link_mask;
+		pci_write_config32(PCI_DEV(0, 1, 0), LCTL2, tmp);
+
+		/* Start link training */
    	tmp = pci_read_config32(PCI_DEV(0, 1, 0), 0xC24) & ~(1 << 16);
    	pci_write_config32(PCI_DEV(0, 1, 0), 0xC24, tmp | (1 << 5));
    }

if (deven & DEVEN_PEG11) {
+		/* Update PEG11 target link speed */
+		tmp = pci_read_config32(PCI_DEV(0, 1, 1), LCAP2);
+		tmp &= link_mask;
+		pci_write_config32(PCI_DEV(0, 1, 1), LCTL2, tmp);
+
+		/* Start link training */
    	tmp = pci_read_config32(PCI_DEV(0, 1, 1), 0xC24) & ~(1 << 16);
    	pci_write_config32(PCI_DEV(0, 1, 1), 0xC24, tmp | (1 << 5));
    }

if (deven & DEVEN_PEG12) {
+		/* Update PEG12 target link speed */
+		tmp = pci_read_config32(PCI_DEV(0, 1, 2), LCAP2);
+		tmp &= link_mask;
+		pci_write_config32(PCI_DEV(0, 1, 2), LCTL2, tmp);
+
+		/* Start link training */
    	tmp = pci_read_config32(PCI_DEV(0, 1, 2), 0xC24) & ~(1 << 16);
    	pci_write_config32(PCI_DEV(0, 1, 2), 0xC24, tmp | (1 << 5));
    }