[coreboot-gerrit] Change in coreboot[master]: soc/intel/{cnl, icl}: Cache the TSEG region

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35026 )

Change subject: soc/intel/{cnl, icl}: Cache the TSEG region
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Patch Set 2:
> Patch Set 2:
>
> 'cbmem -t' from this commit please.

sorry, just to understand your question.

1. do you want to capture the cbmem -t time with this commit as i thought i have captured CB:34995 commit msg already while exposing the new API.

or

2. You wish to get cbmem -t numbers with this CL. Its already shared here right ?

CB:34791
> > With POSTCAR_STAGE=y and (CB:34805 + 34995) [romstage -> postcar -> ramstage]

Total Time till picking kernel: 813,549
Total Time till picking payload: 635,250