Iru Cai (mytbk920423@gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12087
-gerrit
commit 83f7f52b615c02caafb1fcbd28793c4918ad6536 Author: Iru Cai mytbk920423@gmail.com Date: Sun Oct 18 23:40:34 2015 +0800
nb/intel/sandybridge/gma_lvds: support both Sandy&Ivy on one board
Sandy and Ivy Bridge processors use the same socket, and a mainboard with the socket can support both types of CPUs. However, they use different native graphics init code for LVDS and cause a crash if running the wrong code.
This change detects the CPU type and then selects the right code to run. It will add some more code in ramstage.
Tested on a Lenovo T520 with i7-2630qm and i7-3720qm
Signed-off-by: Iru Cai mytbk920423@gmail.com Change-Id: I4624759f9c92d56d547db1ab4b9a1d611a182a91 --- src/northbridge/intel/sandybridge/Makefile.inc | 2 ++ src/northbridge/intel/sandybridge/gma.h | 2 ++ src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c | 4 ++-- src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c | 5 +++++ 4 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index a58d9b1..e551728 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -18,8 +18,10 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE)$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDG ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += gma.c +ramstage-$(CONFIG_IVYBRIDGE_LVDS) += gma_sandybridge_lvds.c ramstage-$(CONFIG_IVYBRIDGE_LVDS) += gma_ivybridge_lvds.c ramstage-$(CONFIG_SANDYBRIDGE_LVDS) += gma_sandybridge_lvds.c +ramstage-$(CONFIG_SANDYBRIDGE_LVDS) += gma_ivybridge_lvds.c
ramstage-y += acpi.c ramstage-y += mrccache.c diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h index 0832468..534b42e 100644 --- a/src/northbridge/intel/sandybridge/gma.h +++ b/src/northbridge/intel/sandybridge/gma.h @@ -117,5 +117,7 @@ struct i915_gpu_controller_info;
int i915lightup_sandy(const struct i915_gpu_controller_info *info, u32 physbase, u16 pio, u8 *mmio, u32 lfb); +int i915lightup_ivy(const struct i915_gpu_controller_info *info, + u32 physbase, u16 pio, u8 *mmio, u32 lfb);
#endif /* NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H */ diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c index 1d7611f..f6818dd 100644 --- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c @@ -153,8 +153,8 @@ static void enable_port(u8 *mmio) read32(mmio + 0xc4000); }
-int i915lightup_sandy(const struct i915_gpu_controller_info *info, - u32 physbase, u16 piobase, u8 *mmio, u32 lfb) +int i915lightup_ivy(const struct i915_gpu_controller_info *info, + u32 physbase, u16 piobase, u8 *mmio, u32 lfb) { int i; u8 edid_data[128]; diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c index e18f146..3b4b64c 100644 --- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c @@ -24,6 +24,7 @@ #include <drivers/intel/gma/i915.h> #include "gma.h" #include "chip.h" +#include "sandybridge.h" #include <pc80/vga.h> #include <pc80/vga_io.h> #include <device/pci_def.h> @@ -142,6 +143,10 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) return 0;
+ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { + return i915lightup_ivy(info, physbase, piobase, mmio, lfb); + } + write32(mmio + 0x00070080, 0x00000000); write32(mmio + DSPCNTR(0), 0x00000000); write32(mmio + 0x00071180, 0x00000000);