[coreboot-gerrit] Change in coreboot[master]: soc/amd/cezanne: FSP: Add UPD entry for eDP tuning

[Bao Zheng (Code Review)]

Attention is currently required from: Jason Glenesk, Nico Huber, Raul Rangel, Marshall Dawson, Paul Menzel, Zheng Bao, Rob Barnes, Felix Held.
Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59918 )

Change subject: soc/amd/cezanne: FSP: Add UPD entry for eDP tuning
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Patch Set 7:

(1 comment)

File src/soc/amd/cezanne/chip.h:

https://review.coreboot.org/c/coreboot/+/59918/comment/a7eb9b33_a4014a2f 
PS7, Line 112: 	uint8_t edp_physel;
> i'd also strongly prefer to use an enum here; same for the corresponding code in picasso. […]

Done.
Add a WIP CL to resolve this. This CL need to be merged.
https://review.coreboot.org/c/coreboot/+/61375