[coreboot-gerrit] Change in coreboot[master]: mainboard/google/volteer: Enable long cr50 ready pulses

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44359 )

Change subject: mainboard/google/volteer: Enable long cr50 ready pulses
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Patch Set 12:

(1 comment)

https://review.coreboot.org/c/coreboot/+/44359/12/src/mainboard/google/volte... 
File src/mainboard/google/volteer/mainboard.c:

https://review.coreboot.org/c/coreboot/+/44359/12/src/mainboard/google/volte... 
PS12, Line 35: mainboard_update_s0ix_disable_mask
> what about a callback like in octopus, 'mainboard_devtree_update` or similar.

Do you want to make the callback from SoC and pass chip config as input to the call? That should be fine. It would still expose the chip config, but updating the devtree configs at runtime requires access to chip config. APL/GLK boards use a callback from SoC, whereas others simply implement a variant_devtree_update() directly from mainboard chip init.