David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58793 )
Change subject: mb/google/brya/var/brask: disabled autonomous GPIO power management ......................................................................
mb/google/brya/var/brask: disabled autonomous GPIO power management
Used H1 firmware where the last version number is 0.0.22, 0.3.22 or less to production that will need to disable autonomous GPIO power management and then can get H1 version by gsctool -a -f -M
BUG=None TEST=emerge-brask coreboot
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: Id9fab5f7d3be74f855e8116ec8f0f24ecc05e0b0 --- M src/mainboard/google/brya/variants/brask/overridetree.cb 1 file changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/58793/1
diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb index 3805666..b20fc99 100644 --- a/src/mainboard/google/brya/variants/brask/overridetree.cb +++ b/src/mainboard/google/brya/variants/brask/overridetree.cb @@ -1,4 +1,15 @@ chip soc/intel/alderlake + # This disabled autonomous GPIO power management, otherwise + # old cr50 FW only supports short pulses; need to clarify + # the minimum PCH IRQ pulse width with Intel, b/180111628 + register "gpio_override_pm" = "1" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_3]" = "0" + register "gpio_pm[COMM_4]" = "0" + register "gpio_pm[COMM_5]" = "0" + device domain 0 on device ref dtt on chip drivers/intel/dptf