Hello Patrick Rudolph, Karthikeyan Ramasubramanian, Vanny E, Kane Chen, Justin TerAvest, Duncan Laurie, build bot (Jenkins), Furquan Shaikh, David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32446
to look at the new patch set (#2).
Change subject: soc/intel: Add GPI interrupt config register offset info ......................................................................
soc/intel: Add GPI interrupt config register offset info
Add the offset information for GPI interrupt status and enable register in the pad_community structure. Populate the concerned information for individual SoCs. This offset information is required to clear the interrupt configuration during the bootup.
BUG=b:130593883 BRANCH=None TEST=Ensure that the interrupt configuration are cleared during bootup. Ensured that the system boots to ChromeOS.
Change-Id: I8af877a734e8d49b700d720b736da8764985a8f8 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/soc/intel/apollolake/gpio_apl.c M src/soc/intel/apollolake/gpio_glk.c M src/soc/intel/apollolake/include/soc/gpio_apl.h M src/soc/intel/apollolake/include/soc/gpio_glk.h M src/soc/intel/cannonlake/gpio.c M src/soc/intel/cannonlake/gpio_cnp_h.c M src/soc/intel/cannonlake/include/soc/gpio_defs.h M src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h M src/soc/intel/common/block/include/intelblocks/gpio.h M src/soc/intel/denverton_ns/gpio.c M src/soc/intel/icelake/gpio.c M src/soc/intel/icelake/include/soc/gpio_defs.h M src/soc/intel/skylake/gpio.c M src/soc/intel/skylake/include/soc/gpio_defs.h 14 files changed, 76 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/32446/2