[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Add GPIOs for Alder Lake SOC

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )

Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC
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Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... 
File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:

https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... 
PS2, Line 309:
> and don't expect even FSP also does those programming as well.

Sorry, I can't parse that. Do you mean "FSP does not program these GPIOs" (vGPIO for example?) If yes, then this is untrue - for CNL as well as ICL, TGL and probably ADL.
> Any GPIO with PIN MUX feature FSP has UPD to ignore FSP to program, for example: if I2C3 doesn't have device attached on board we make the UPD disable

Well, FSP in some cases does nothing more than setting NF1, which coreboot can, too.