Furquan Shaikh (furquan@google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17205
-gerrit
commit d242beb6e61e8fcf3c64eedbc9c5b8d4689af225 Author: Furquan Shaikh furquan@chromium.org Date: Tue Nov 1 21:33:12 2016 -0700
soc/intel/apollolake: Implement SPI flash status register read
This was a dummy implementation until now which returned -1 always. Add support for reading SPI flash status register (srp0).
BUG=chrome-os-partner:59267 BRANCH=None TEST=Verified by enabling and disabling write-protect on reef that the value of SRP0 changes accordingly in status register read.
Change-Id: Ib1349605dd87c4a087e416f52a8256b1eaac4f4c Signed-off-by: Furquan Shaikh furquan@chromium.org --- src/soc/intel/apollolake/spi.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c index 85bc0b6..8cb8aa5 100644 --- a/src/soc/intel/apollolake/spi.c +++ b/src/soc/intel/apollolake/spi.c @@ -313,8 +313,16 @@ static int nuclear_spi_write(struct spi_flash *flash,
static int nuclear_spi_status(struct spi_flash *flash, uint8_t *reg) { - printk(BIOS_DEBUG, "NOT IMPLEMENTED: %s() !!!\n", __func__); - return E_NOT_IMPLEMENTED; + int ret; + BOILERPLATE_CREATE_CTX(ctx); + + ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_RD_STATUS, 0, + sizeof(*reg)); + if (ret != SUCCESS) + return ret; + + drain_xfer_fifo(ctx, reg, sizeof(*reg)); + return ret; }
static struct spi_slave boot_spi CAR_GLOBAL;