Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85434?usp=email )
Change subject: soc/intel/xeon_xp: Remove 1 bytes losing in lower DRAM ......................................................................
soc/intel/xeon_xp: Remove 1 bytes losing in lower DRAM
Generally the base address of FSP output is already aligned so there is no need to minus 1. The current code loses 1 byte in the lower DRAM address space.
Change-Id: Ia8147702aad496c431cf10b896d68a826c9e45b1 Signed-off-by: Yuchi Chen yuchi.chen@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/85434 Reviewed-by: Jincheng Li jincheng.li@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Shuo Liu shuo.liu@intel.com --- M src/soc/intel/xeon_sp/uncore.c 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Shuo Liu: Looks good to me, approved Jincheng Li: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 1d77675..93677b9 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -268,7 +268,7 @@
/* 1MB -> top_of_ram */ fsp_find_reserved_memory(&fsp_mem); - top_of_ram = range_entry_base(&fsp_mem) - 1; + top_of_ram = range_entry_base(&fsp_mem); res = ram_from_to(dev, index++, 1 * MiB, top_of_ram); LOG_RESOURCE("low_ram", dev, res);