[coreboot-gerrit] Change in coreboot[master]: soc/amd/cezanne: use common TSC and monotonic timer code

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48306 )

Change subject: soc/amd/cezanne: use common TSC and monotonic timer code
......................................................................

soc/amd/cezanne: use common TSC and monotonic timer code

Change-Id: I9bc82f1e64f2cf21bfa4bf1ac75d17247208686c
Signed-off-by: Felix Held 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48306
Reviewed-by: Marshall Dawson 
Tested-by: build bot (Jenkins) 
---
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/cezanne/Makefile.inc
D src/soc/amd/cezanne/timer.c
3 files changed, 1 insertion(+), 10 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Marshall Dawson: Looks good to me, approved

diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 6900ad7..914384b 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -17,8 +17,7 @@
    select SOC_AMD_COMMON
    select SOC_AMD_COMMON_BLOCK_NONCAR
    select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
-	select NO_MONOTONIC_TIMER		# TODO: replace
-	select UNKNOWN_TSC_RATE			# TODO: replace
+	select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H

config EARLY_RESERVED_DRAM_BASE
    hex
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index d1d8e97..d4f585f 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -7,7 +7,6 @@
 romstage-y	+= romstage.c

ramstage-y	+= chip.c
-ramstage-y	+= timer.c

CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include

diff --git a/src/soc/amd/cezanne/timer.c b/src/soc/amd/cezanne/timer.c
deleted file mode 100644
index 9054ffd..0000000
--- a/src/soc/amd/cezanne/timer.c
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <delay.h>
-
-void init_timer(void)
-{
-}