[coreboot-gerrit] [XS] Change in coreboot[main]: mb/google/rauru: Add EC suspend pin initial setting

[Yu-Ping Wu (Code Review)]

Attention is currently required from: Hung-Te Lin, Jarried Lin.

Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86381?usp=email )

Change subject: mb/google/rauru: Add EC suspend pin initial setting
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Patch Set 3:

(3 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/86381/comment/de3be7e3_9b1d97c3?usp... :
PS3, Line 7: mb/google/rauru: Add EC suspend pin initial setting
           : 
           : Set the EC suspend pin to output high.
> Please revise the commit message. And the purpose of the setting.

In particular, why do we not need this for previous SoCs such as geralt?

File src/mainboard/google/rauru/chromeos.c:

https://review.coreboot.org/c/coreboot/+/86381/comment/d63c0b06_e9a38894?usp... :
PS3, Line 22: 	gpio_output(GPIO_EC_SUSPEND_PIN, 1);
In ATF plat/mediatek/drivers/spm/mt8196/mt_spm_suspend.c, we set the GPIO mode and direction for `EC_SUSPEND_BK_PIN`. Should we do the same for `EC_SUSPEND_PIN` in ATF instead of (or in addition to) here for consistency?

File src/mainboard/google/rauru/gpio.h:

https://review.coreboot.org/c/coreboot/+/86381/comment/66a8b0bb_ffbdc2cf?usp... :
PS3, Line 8: _OD
Not related to this patch, but what's `_OD`? The name on the schematics is `BEEP_ON`. Could you upload a separate patch to fix this?